Reviewed-by: Abdul Lateef Attar <abdattar@amd.com>
From: abnchang <abnchang@amd.com>
BZ#: 4471
Update definitions according to PI spec 1.8 errata A
Signed-off-by: Abner Chang <abner.chang@amd.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Abdul Lateef Attar <abdattar@amd.com>
Cc: Brit Chesley <brit.chesley@amd.com>
---
MdePkg/Include/Protocol/SpiConfiguration.h | 10 +++++++++-
MdePkg/Include/Protocol/SpiHc.h | 16 +++++++++++++++-
MdePkg/Include/Protocol/SpiIo.h | 12 +++++++++++-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Protocol/SpiConfiguration.h b/MdePkg/Include/Protocol/SpiConfiguration.h
index 3f8fb9ff62c..120b54bbad8 100644
--- a/MdePkg/Include/Protocol/SpiConfiguration.h
+++ b/MdePkg/Include/Protocol/SpiConfiguration.h
@@ -2,10 +2,11 @@
This file defines the SPI Configuration Protocol.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- This Protocol was introduced in UEFI PI Specification 1.6.
+ This Protocol was introduced in UEFI PI Specification 1.8 A.
**/
@@ -168,6 +169,13 @@ typedef struct _EFI_SPI_BUS {
VOID *ClockParameter;
} EFI_SPI_BUS;
+///
+/// Definitions of SPI Part Attributes.
+///
+#define SPI_PART_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0
+#define SPI_PART_SUPPORTS_4_B1T_DATA_BUS_WIDTH BIT1
+#define SPI_PART_SUPPORTS_8_B1T_DATA_BUS_WIDTH BIT2
+
///
/// The EFI_SPI_PERIPHERAL data structure describes how a specific block of
/// logic which is connected to the SPI bus. This data structure also selects
diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiHc.h
index 30128dd5c4d..354de721606 100644
--- a/MdePkg/Include/Protocol/SpiHc.h
+++ b/MdePkg/Include/Protocol/SpiHc.h
@@ -2,10 +2,11 @@
This file defines the SPI Host Controller Protocol.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- This Protocol was introduced in UEFI PI Specification 1.6.
+ This Protocol was introduced in UEFI PI Specification 1.8 A.
**/
@@ -121,6 +122,19 @@ typedef EFI_STATUS
IN EFI_SPI_BUS_TRANSACTION *BusTransaction
);
+///
+/// Definitions of SPI Host Controller Attributes.
+///
+#define HC_SUPPORTS_WRITE_ONLY_OPERATIONS BIT0
+#define HC_SUPPORTS_READ_ONLY_OPERATIONS BIT1
+#define HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS BIT2
+#define HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT3
+#define HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS BIT4
+#define HC_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT5
+#define HC_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT6
+#define HC_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT7
+#define HC_TRANSFER_SIZE_INCLUDES_OPCODE BIT8
+#define HC_TRANSFER_SIZE_INCLUDES_ADDRESS BIT9
///
/// Support a SPI data transaction between the SPI controller and a SPI chip.
///
diff --git a/MdePkg/Include/Protocol/SpiIo.h b/MdePkg/Include/Protocol/SpiIo.h
index b4fc5e03b88..2c95a375a20 100644
--- a/MdePkg/Include/Protocol/SpiIo.h
+++ b/MdePkg/Include/Protocol/SpiIo.h
@@ -2,10 +2,11 @@
This file defines the SPI I/O Protocol.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
- This Protocol was introduced in UEFI PI Specification 1.6.
+ This Protocol was introduced in UEFI PI Specification 1.8 A.
**/
@@ -223,6 +224,15 @@ typedef struct _EFI_SPI_BUS_TRANSACTION {
UINT8 *ReadBuffer;
} EFI_SPI_BUS_TRANSACTION;
+///
+/// Definitions of SPI I/O Attributes.
+///
+#define SPI_IO_SUPPORTS_2_BIT_DATA_BUS_WIDTH BIT0
+#define SPI_IO_SUPPORTS_4_BIT_DATA_BUS_WIDTH BIT1
+#define SPI_IO_SUPPORTS_8_BIT_DATA_BUS_WIDTH BIT2
+#define SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE BIT3
+#define SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS BIT4
+
///
/// Support managed SPI data transactions between the SPI controller and a SPI
/// chip.