From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.65; helo=hqemgate16.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate16.nvidia.com (hqemgate16.nvidia.com [216.228.121.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0CA321A07A80 for ; Thu, 8 Nov 2018 09:51:07 -0800 (PST) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 08 Nov 2018 09:51:16 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 08 Nov 2018 09:51:07 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 08 Nov 2018 09:51:07 -0800 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 8 Nov 2018 17:51:07 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 8 Nov 2018 17:51:06 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 8 Nov 2018 17:51:06 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 08 Nov 2018 09:51:06 -0800 From: Jeff Brasen To: CC: Jeff Brasen , Ard Biesheuvel , Leif Lindholm , "Grish Pathak" Date: Thu, 8 Nov 2018 10:50:44 -0700 Message-ID: <6dbe50db1293266db7588630fc97328276e82843.1541699412.git.jbrasen@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1541699476; bh=QJtMvSXfiqKc9ReiPu3KNe7B/YFbnAlDBaOJAk+8Yo4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=CmT/MHwq5xZS2Y5hjUnvfbGtxJsVEuWSB3qHiHC/yDMn2LtUHcIlX2WGTznCZ0dqe D9c7lXfYvsKw0ghyTP6/KXPcnokGpIT2ceAVUT5+TwHX2VMuQytT59tZL8Q/iua6yu hOOVIGSO8rZn3+0xfU/KxI08ONs9fhuoqt9MNej/FuRvJFTNvAOPan2qFC03p9Nls8 NOXPD1NuIJ7IwWX04wSJzd5satCAGJbE25FYMlbRMsNeIbIxjKrCwBnV6lPbbKzuOW bexr+QCYpN1JmXR26JhtaFv2FPtuTuL2yD4hix2RxseRkofZoHe9SgbakSC+5Zptzn ZT2msOuRNRMQQ== Subject: [PATCH] ArmPkg/ArmScmiDxe: Add clock enable function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Nov 2018 17:51:07 -0000 Content-Type: text/plain Add function to allow enabling and disabling of the clock using the SCMI interface. Update the protocol GUID as the protocol interface has changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Grish Pathak --- ArmPkg/ArmPkg.dec | 2 +- .../ArmScmiDxe/ArmScmiClockProtocolPrivate.h | 7 +++ ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c | 50 +++++++++++++++++++++- ArmPkg/Include/Protocol/ArmScmiClockProtocol.h | 21 ++++++++- 4 files changed, 77 insertions(+), 3 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 84e57a0..a7b55a1 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -57,7 +57,7 @@ ## Arm System Control and Management Interface(SCMI) Clock management protocol ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h - gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } } + gArmScmiClockProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } } ## Arm System Control and Management Interface(SCMI) Clock management protocol ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h index 0d1ec6f..c135bac 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h @@ -59,6 +59,13 @@ typedef struct { CLOCK_RATE_DWORD Rate; } CLOCK_RATE_SET_ATTRIBUTES; + +// Message parameters for CLOCK_CONFIG_SET command. +typedef struct { + UINT32 ClockId; + UINT32 Attributes; +} CLOCK_CONFIG_SET_ATTRIBUTES; + // if ClockAttr Bit[0] is set then clock device is enabled. #define CLOCK_ENABLE_MASK 0x1 #define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1) diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c index 64d2afa..493eb45 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c @@ -388,6 +388,53 @@ ClockRateSet ( return Status; } +/** Enable/Disable specified clock. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Enable TRUE to enable, FALSE to disable. + + @retval EFI_SUCCESS Clock enable/disable successful. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockEnable ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + IN BOOLEAN Enable + ) +{ + EFI_STATUS Status; + CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes); + if (EFI_ERROR (Status)) { + return Status; + } + + // Fill arguments for clock protocol command. + ClockConfigSetAttributes->ClockId = ClockId; + ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0; + + Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET; + + PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES); + + // Execute and wait for response on a SCMI channel. + Status = ScmiCommandExecute ( + &Cmd, + &PayloadLength, + NULL + ); + + return Status; +} + // Instance of the SCMI clock management protocol. STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = { ClockGetVersion, @@ -395,7 +442,8 @@ STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = { ClockGetClockAttributes, ClockDescribeRates, ClockRateGet, - ClockRateSet + ClockRateSet, + ClockEnable }; /** Initialize clock management protocol and install protocol on a given handle. diff --git a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h index 3db26cb..d367f37 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h @@ -21,7 +21,7 @@ #include #define ARM_SCMI_CLOCK_PROTOCOL_GUID { \ - 0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \ + 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \ } extern EFI_GUID gArmScmiClockProtocolGuid; @@ -205,6 +205,24 @@ EFI_STATUS IN UINT64 Rate ); +/** Enable/Disable specified clock. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Enable TRUE to enable, FALSE to disable. + + @retval EFI_SUCCESS Clock enable/disable successful. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_ENABLE) ( + IN SCMI_CLOCK_PROTOCOL *This, + IN UINT32 ClockId, + IN BOOLEAN Enable + ); + typedef struct _SCMI_CLOCK_PROTOCOL { SCMI_CLOCK_GET_VERSION GetVersion; SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks; @@ -212,6 +230,7 @@ typedef struct _SCMI_CLOCK_PROTOCOL { SCMI_CLOCK_DESCRIBE_RATES DescribeRates; SCMI_CLOCK_RATE_GET RateGet; SCMI_CLOCK_RATE_SET RateSet; + SCMI_CLOCK_ENABLE Enable; } SCMI_CLOCK_PROTOCOL; #endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */ -- 2.7.4