From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3A4EF1A1E72 for ; Fri, 21 Oct 2016 01:02:48 -0700 (PDT) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8BDFBC067C1B; Fri, 21 Oct 2016 08:02:47 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-45.phx2.redhat.com [10.3.116.45]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u9L82jCf026859; Fri, 21 Oct 2016 04:02:46 -0400 To: Dennis Chen , edk2-devel@ml01.01.org References: <1477029024-31932-1-git-send-email-dennis.chen@arm.com> Cc: nd@arm.com, Leif Lindholm , Ard Biesheuvel From: Laszlo Ersek Message-ID: <6e4f61bc-fdc0-a08c-c38a-b9e7696b5a2b@redhat.com> Date: Fri, 21 Oct 2016 10:02:45 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1477029024-31932-1-git-send-email-dennis.chen@arm.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 21 Oct 2016 08:02:47 +0000 (UTC) Subject: Re: [RESEND PATCH] ArmVirtPkg: Bit width adaption in ASSERT() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Oct 2016 08:02:48 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 10/21/16 07:50, Dennis Chen wrote: > Since All the GIC base address variables has been aligned to 64-bit, it > doesn't make sense to continue use MAX_UINT32 in ASSERT() statement, so > this patch uses MAX_UINTN to adapt to this kind of change. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Laszlo Ersek > Signed-off-by: Dennis Chen > --- > ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > index 64afc4d..6488061 100644 > --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c > @@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor ( > > // RegProp[0..1] == { GICD base, GICD size } > DistBase = SwapBytes64 (Reg[0]); > - ASSERT (DistBase < MAX_UINT32); > + ASSERT (DistBase < MAX_UINTN); > > // RegProp[2..3] == { GICR base, GICR size } > RedistBase = SwapBytes64 (Reg[2]); > - ASSERT (RedistBase < MAX_UINT32); > + ASSERT (RedistBase < MAX_UINTN); > > PcdSet64 (PcdGicDistributorBase, DistBase); > PcdSet64 (PcdGicRedistributorsBase, RedistBase); > @@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor ( > > DistBase = SwapBytes64 (Reg[0]); > CpuBase = SwapBytes64 (Reg[2]); > - ASSERT (DistBase < MAX_UINT32); > - ASSERT (CpuBase < MAX_UINT32); > + ASSERT (DistBase < MAX_UINTN); > + ASSERT (CpuBase < MAX_UINTN); > > PcdSet64 (PcdGicDistributorBase, DistBase); > PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase); > Ard, can you please handle this iteration of the patch as well? I do have one suggestion, for the subject: ArmVirtPkg/ArmVirtGicArchLib: adapt ASSERT()s to 64-bit base addresses If you guys agree, I think it can be done on commit. With that, Acked-by: Laszlo Ersek Thanks Laszlo