From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=QA17K0V0; spf=pass (domain: redhat.com, ip: 207.211.31.120, mailfrom: philmd@redhat.com) Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.120]) by groups.io with SMTP; Tue, 01 Oct 2019 01:44:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1569919494; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2et2XQ4pKiw7P5i4TPouo0wVq1ABjDOlBZvtIIrrmK8=; b=QA17K0V0VMMKwF6e/1qtXShhq6ruOw7PQexqLpj+uUsdjfZeLnw8uXuPAzJFAhrUXiNh7u uB2edDXI4n+LwLVBkOO206/t9rdORXC/XRCd5wR+hsR9y9Gpy2qQv1/CJcwWFoWQPy6/k7 JWM9eeNJD3BN8dkyT/Ou0q0mWyesHRs= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-347-LN7fj8UWMRqGaHxQs450Rw-1; Tue, 01 Oct 2019 04:44:52 -0400 Received: by mail-wr1-f69.google.com with SMTP id a4so5666428wrg.8 for ; Tue, 01 Oct 2019 01:44:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=UnxwP0IWMu6OiTrvyMt9sJ2rs8yq9YKjJ0pknoaPLV0=; b=tksHqvae1Z4o+9Whx+6FO8z7QOD5fITQKlpaqp1cKkAr2k9/KfUjXauH3XG8sEw4HR t8bRyZj0AXKHgxQBVvbaersr2i3INv4l6EiKS0YTrI5J4e+tfb4rzs0i4HRa0M931LxL /g7wxaeBbPtfs4UH66YfFJi8/sBNtfGWbjsdaefpqxgnjwd47MxE5ItNyXGPa9tUitLd RmzZqQCIxYdsyn/T0VDzRdwo5j/j9NoYwiKLt0sJUMl6DyGqM/9DYARQmbJHz7sOcSdj 5zIWlSE8jGOLarfLGK2uCYWR85XG4+EELH95qiy6pEsEjeu60m16vbGjNgJ8OLixJMnA Lj3g== X-Gm-Message-State: APjAAAUo03mFl0rYY4yXphecjimEzj18+6yA8CZkq7SpPbUlSkV7Ddls s7/S4SGKF6toumw7mnvBpECRMUNDdD0RKnKrMMogtOhS6s7osjOn3Nm3AETofnMWEC+KZ+ZtURk yvk44EiH9yVN/Kw== X-Received: by 2002:a7b:c44d:: with SMTP id l13mr2620939wmi.171.1569919491543; Tue, 01 Oct 2019 01:44:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqw65hLyH6rQPS2U/QBOZ+RspGv0Kw4vLX1w50bYpx0YdkGVP+CO0/BKSVQ9/YvG9YP92mPT1A== X-Received: by 2002:a7b:c44d:: with SMTP id l13mr2620925wmi.171.1569919491217; Tue, 01 Oct 2019 01:44:51 -0700 (PDT) Return-Path: Received: from [192.168.1.35] (240.red-88-21-68.staticip.rima-tde.net. [88.21.68.240]) by smtp.gmail.com with ESMTPSA id e17sm1962701wma.15.2019.10.01.01.44.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Oct 2019 01:44:50 -0700 (PDT) Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v2 08/29] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation. To: devel@edk2.groups.io, abner.chang@hpe.com References: <1569198715-31552-1-git-send-email-abner.chang@hpe.com> <1569198715-31552-9-git-send-email-abner.chang@hpe.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Message-ID: <6e642bc0-bbda-aac9-6f08-0ebdc33b643b@redhat.com> Date: Tue, 1 Oct 2019 10:44:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.0 MIME-Version: 1.0 In-Reply-To: <1569198715-31552-9-git-send-email-abner.chang@hpe.com> X-MC-Unique: LN7fj8UWMRqGaHxQs450Rw-1 X-Mimecast-Spam-Score: 0 Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable On 9/23/19 2:31 AM, Abner Chang wrote: > Implement RISC-V cache maintenance functions in > BaseCacheMaintenanceLib. >=20 > Signed-off-by: Abner Chang > --- > .../BaseCacheMaintenanceLib.inf | 4 + > .../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 ++++++++++++++= +++++++ > 2 files changed, 254 insertions(+) > create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >=20 > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceL= ib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > index ec7feec..d9bfa04 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > @@ -6,6 +6,7 @@ > # > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved. > # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<= BR> > +# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All ri= ghts reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -41,6 +42,9 @@ > [Sources.AARCH64] > ArmCache.c > =20 > +[Sources.RISCV64] > + RiscVCache.c > + > [Packages] > MdePkg/MdePkg.dec > =20 > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg= /Library/BaseCacheMaintenanceLib/RiscVCache.c > new file mode 100644 > index 0000000..d8e4665 > --- /dev/null > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -0,0 +1,250 @@ > +/** @file > + RISC-V specific functionality for cache. > + > + Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. = All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + RISC-V invalidate instruction cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateInstCacheAsm ( > + VOID > + ); > + > +/** > + RISC-V invalidate data cache. > + > +**/ > +VOID > +EFIAPI > +RiscVInvalidateDataCacheAsm ( > + VOID > + ); > + > +/** > + Invalidates the entire instruction cache in cache coherency domain of = the > + calling CPU. > + > +**/ > +VOID > +EFIAPI > +InvalidateInstructionCache ( > + VOID > + ) > +{ > + RiscVInvalidateInstCacheAsm (); > +} > + > +/** > + Invalidates a range of instruction cache lines in the cache coherency = domain > + of the calling CPU. > + > + Invalidates the instruction cache lines specified by Address and Lengt= h. If > + Address is not aligned on a cache line boundary, then entire instructi= on > + cache line containing Address is invalidated. If Address + Length is n= ot > + aligned on a cache line boundary, then the entire instruction cache li= ne > + containing Address + Length -1 is invalidated. This function may choos= e to > + invalidate the entire instruction cache if that is more efficient than > + invalidating the specified range. If Length is 0, then no instruction = cache > + lines are invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the instruction cache lines to > + invalidate. If the CPU is in a physical addressing mod= e, then > + Address is a physical address. If the CPU is in a virt= ual > + addressing mode, then Address is a virtual address. > + > + @param Length The number of bytes to invalidate from the instruction= cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateInstructionCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)= ); > + return Address; > +} > + > +/** > + Writes back and invalidates the entire data cache in cache coherency d= omain > + of the calling CPU. > + > + Writes back and invalidates the entire data cache in cache coherency d= omain > + of the calling CPU. This function guarantees that all dirty cache line= s are > + written back to system memory, and also invalidates all the data cache= lines > + in the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackInvalidateDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__)= ); > +} > + > +/** > + Writes back and invalidates a range of data cache lines in the cache > + coherency domain of the calling CPU. > + > + Writes back and invalidates the data cache lines specified by Address = and > + Length. If Address is not aligned on a cache line boundary, then entir= e data > + cache line containing Address is written back and invalidated. If Addr= ess + > + Length is not aligned on a cache line boundary, then the entire data c= ache > + line containing Address + Length -1 is written back and invalidated. T= his > + function may choose to write back and invalidate the entire data cache= if > + that is more efficient than writing back and invalidating the specifie= d > + range. If Length is 0, then no data cache lines are written back and > + invalidated. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write back= and > + invalidate. If the CPU is in a physical addressing mod= e, then > + Address is a physical address. If the CPU is in a virt= ual > + addressing mode, then Address is a virtual address. > + @param Length The number of bytes to write back and invalidate from = the > + data cache. > + > + @return Address of cache invalidation. > + > +**/ > +VOID * > +EFIAPI > +WriteBackInvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__= )); typo unsupportted -> unsupported > + return Address; > +} > + > +/** > + Writes back the entire data cache in cache coherency domain of the cal= ling > + CPU. > + > + Writes back the entire data cache in cache coherency domain of the cal= ling > + CPU. This function guarantees that all dirty cache lines are written b= ack to > + system memory. This function may also invalidate all the data cache li= nes in > + the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +EFIAPI > +WriteBackDataCache ( > + VOID > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__= )); Ditto, > +} > + > +/** > + Writes back a range of data cache lines in the cache coherency domain = of the > + calling CPU. > + > + Writes back the data cache lines specified by Address and Length. If A= ddress > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is written back. If Address + Length is not aligned= on a > + cache line boundary, then the entire data cache line containing Addres= s + > + Length -1 is written back. This function may choose to write back the = entire > + data cache if that is more efficient than writing back the specified r= ange. > + If Length is 0, then no data cache lines are written back. This functi= on may > + also invalidate all the data cache lines in the specified range of the= cache > + coherency domain of the calling CPU. Address is returned. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to write back= . If > + the CPU is in a physical addressing mode, then Address= is a > + physical address. If the CPU is in a virtual addressin= g > + mode, then Address is a virtual address. > + @param Length The number of bytes to write back from the data cache. > + > + @return Address of cache written in main memory. > + > +**/ > +VOID * > +EFIAPI > +WriteBackDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__= )); Ditto, > + return Address; > +} > + > +/** > + Invalidates the entire data cache in cache coherency domain of the cal= ling > + CPU. > + > + Invalidates the entire data cache in cache coherency domain of the cal= ling > + CPU. This function must be used with care because dirty cache lines ar= e not > + written back to system memory. It is typically used for cache diagnost= ics. If > + the CPU does not support invalidation of the entire data cache, then a= write > + back and invalidate operation should be performed on the entire data c= ache. > + > +**/ > +VOID > +EFIAPI > +InvalidateDataCache ( > + VOID > + ) > +{ > + RiscVInvalidateDataCacheAsm (); > +} > + > +/** > + Invalidates a range of data cache lines in the cache coherency domain = of the > + calling CPU. > + > + Invalidates the data cache lines specified by Address and Length. If A= ddress > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is invalidated. If Address + Length is not aligned = on a > + cache line boundary, then the entire data cache line containing Addres= s + > + Length -1 is invalidated. This function must never invalidate any cach= e lines > + outside the specified range. If Length is 0, then no data cache lines = are > + invalidated. Address is returned. This function must be used with care > + because dirty cache lines are not written back to system memory. It is > + typically used for cache diagnostics. If the CPU does not support > + invalidation of a data cache range, then a write back and invalidate > + operation should be performed on the data cache range. > + > + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > + > + @param Address The base address of the data cache lines to invalidate= . If > + the CPU is in a physical addressing mode, then Address= is a > + physical address. If the CPU is in a virtual addressin= g mode, > + then Address is a virtual address. > + @param Length The number of bytes to invalidate from the data cache. > + > + @return Address. > + > +**/ > +VOID * > +EFIAPI > +InvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +{ > + DEBUG((DEBUG_ERROR, "%a:RISC-V unsupportted function.\n", __FUNCTION__= )); Ditto. > + return Address; > +} >=20