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X-MS-Exchange-AntiSpam-MessageData: 6sKoHn4h2iJtnhSoS0snoSpd2KvLmvYy+XZcxi92HF+AZKfK3igXc3Uhacwq7yZU9ouc9tTKXfrdmVjd+9+lTXNoNB7CrPkK3WSkdtirjK5xUBEJUyjqxQtRM/PWQnLYEcXjaVFLIus2D7+r01aGR5z35JhgzlwxA/hW+EE/WJOuQb7YxVHpFbvZNLXEHB3IXshRQDWk9quKoMCp3GZOwBHQ32r4BZGowK+I9VRvu53K6BNNRHu6NRadT06eJMZ5FLEKvvRgi3OZ4Vid5/oVDg66lceRJqIEWL6p4ApqDMMMNIyiwBPEbU66D78gd2dIuXg9gu8bdXUjAL9+W0Lg6soIzLWFEy2eL9EQoYiZQ/Ni9SjvVckT5TD+7C5NzBye7tTWgEnZsmRHyLDU9DdFXyBnY3Ar8eCXFqQ+UgqDGgIl0ZDvTddQ7fst8bDvP9YxF7Fky7yx0wYJ3y/1mwWHARH47rtd89EgTXTmVvnFZYU= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 859f1792-1a73-4976-2692-08d7fc3ed908 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2020 21:51:55.7195 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SBRWNtnK332Kf1cUQcDXmBHW2Lec9RPQ7/oD+XNMI1sVEl7e8jYRrTkBptRK5l/5nrstJcES8uq0x/AcxcWUUA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2504 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a DR7 read or write intercept generates a #VC exception. The #VC handler must provide special support to the guest for this. On a DR7 write, the #VC handler must cache the value and issue a VMGEXIT to notify the hypervisor of the write. However, the #VC handler must not actually set the value of the DR7 register. On a DR7 read, the #VC handler must return the cached value of the DR7 register to the guest. VMGEXIT is not invoked for a DR7 register read. To avoid exception recursion, a #VC exception will not try to read and push the actual debug registers into the EFI_SYSTEM_CONTEXT_X64 struct and instead push zeroes. The #VC exception handler does not make use of the debug registers from saved context. Cc: Eric Dong Cc: Ray Ni Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Signed-off-by: Tom Lendacky --- .../Library/VmgExitLib/X64/VmgExitVcHandler.c | 105 ++++++++++++++++++ .../X64/ExceptionHandlerAsm.nasm | 17 +++ .../X64/Xcode5ExceptionHandlerAsm.nasm | 17 +++ 3 files changed, 139 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/X64/VmgExitVcHandler.c b/OvmfPkg/Library/VmgExitLib/X64/VmgExitVcHandler.c index b028b20f255a..e4072d79d704 100644 --- a/OvmfPkg/Library/VmgExitLib/X64/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/X64/VmgExitVcHandler.c @@ -14,6 +14,16 @@ #define CR4_OSXSAVE (1 << 18) +#define DR7_RESET_VALUE 0x400 + +// +// Per-CPU data mapping structure +// +typedef struct { + BOOLEAN Dr7Cached; + UINT64 Dr7; +} SEV_ES_PER_CPU_DATA; + // // Instruction execution mode definition // @@ -1494,6 +1504,93 @@ RdtscExit ( return 0; } +/** + Handle a DR7 register write event. + + Use the VMGEXIT instruction to handle a DR7 write event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @retval Others New exception value to propagate + +**/ +STATIC +UINT64 +Dr7WriteExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + SEV_ES_PER_CPU_DATA *SevEsData; + INTN *Register; + UINT64 Status; + + Ext = &InstructionData->Ext; + SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + + /* Using a value of 0 for ExitInfo1 means RAX holds the value */ + Ghcb->SaveArea.Rax = *Register; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status = VmgExit (Ghcb, SVM_EXIT_DR7_WRITE, 0, 0); + if (Status) { + return Status; + } + + SevEsData->Dr7 = *Register; + SevEsData->Dr7Cached = TRUE; + + return 0; +} + +/** + Handle a DR7 register read event. + + Use the VMGEXIT instruction to handle a DR7 read event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + +**/ +STATIC +UINT64 +Dr7ReadExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + SEV_ES_PER_CPU_DATA *SevEsData; + INTN *Register; + + Ext = &InstructionData->Ext; + SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + *Register = (SevEsData->Dr7Cached) ? SevEsData->Dr7 : DR7_RESET_VALUE; + + return 0; +} + /** Handle a #VC exception. @@ -1538,6 +1635,14 @@ VmgExitHandleVc ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_DR7_READ: + NaeExit = Dr7ReadExit; + break; + + case SVM_EXIT_DR7_WRITE: + NaeExit = Dr7WriteExit; + break; + case SVM_EXIT_RDTSC: NaeExit = RdtscExit; break; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 3814f9de3703..2a5545ecfd41 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -224,6 +226,9 @@ HasErrorCode: push rax ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -236,7 +241,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm index 19198f273137..26cae56cc5cf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -225,6 +227,9 @@ HasErrorCode: push rax ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -237,7 +242,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp -- 2.17.1