From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM02-CY1-obe.outbound.protection.outlook.com (NAM02-CY1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.13475.1574280499527396450 for ; Wed, 20 Nov 2019 12:08:20 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@amdcloud.onmicrosoft.com header.s=selector2-amdcloud-onmicrosoft-com header.b=uALEGK3z; spf=none, err=SPF record not found (domain: amd.com, ip: , mailfrom: thomas.lendacky@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=D62pQQO2m5lHPz4GqxQdgiz2c4I1E39SoveCbv00v52OWEzDmBMuEXVu/8c/5TQVzL6g7CE4j1sTzbjJCBb9RzCwE0Fl1PakP62CBD94b5Nu+UCN+FskNHyY2Kefp2oJaN3/fwhGweVBChwE6yU7YDRedmPWYJUvOWpzJS4h2wN0jam2EulHs/1X9N9s6RylQyqTOZHk6BV2h9MubaJbTmw5h3lHe1HDgdcdo20+ftJjjXSFHO1edORam5yev1ITA5Vsc9cw/xfhiK4uI0/x71rZOc3Lbv/7J00LVuxgufHjkiwdqU8inmCJ+i3/T5bkFrb0BGp8iC4ZrjiUrIfDkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LGS8EU+cWS2ozHJvHVfFgMED5b6m7aBtoRsPGIbY+A4=; b=bE6ZMfICM68IqLQ1xs1FmAwL/M0RPswL9lrjtvDVTvJ+xEYm+1Z7C2pag9DmIww9Mfxi/n2a1/PpzVlaz+0iF5jXZRjCKkTmDoIMqNKeexZ2dlVhK1CDRhOJ5yw0EnotjBlc1MrDes9s6suAv4KWnKJ0OH05eNvv9XcaMd/gNURfCbgeib+KM9eGYV8+/+zYIG6mF5K0eoBuMqCfvWzS1QMmf4jMOrJZnYtUNYdsF/DxXoroFrIcHopyG/bMYBIva6rSuREcZFZYf98HGke5ZlxBjgxrIWPlpDyFIAUTbrhlLsUGBioTTbkg0gyaibAgffML7H+qciUCzNnBoNGagA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LGS8EU+cWS2ozHJvHVfFgMED5b6m7aBtoRsPGIbY+A4=; b=uALEGK3zKCRLZcLzdJ28yWHXmi46V+F9bNcvselN966c3P8HSN1pA2sh2IKZzC1pR6P/W/4Uc/zvDsq7FPhahqbJQcsuE0qKcAdRdb7FEoi8OULZkBw/8My/f/xCctM8ss1UArlnEk4dbb4ogb6thhhn9I5iZjBnUALJI40Haes= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; Received: from DM6PR12MB3163.namprd12.prod.outlook.com (20.179.71.154) by DM6PR12MB3675.namprd12.prod.outlook.com (10.255.76.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2451.28; Wed, 20 Nov 2019 20:08:19 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::dd0c:8e53:4913:8ef4]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::dd0c:8e53:4913:8ef4%5]) with mapi id 15.20.2451.031; Wed, 20 Nov 2019 20:08:19 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [RFC PATCH v3 34/43] UefiCpuPkg: Add a 16-bit protected mode code segment descriptor Date: Wed, 20 Nov 2019 14:06:56 -0600 Message-Id: <711d2a5db836355881ea22bb5210ca5714bd60d2.1574280425.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM3PR12CA0087.namprd12.prod.outlook.com (2603:10b6:0:57::31) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4121a2b6-b9c2-474b-6195-08d76df5520d X-MS-TrafficTypeDiagnostic: DM6PR12MB3675: X-MS-Exchange-PUrlCount: 1 X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 02272225C5 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(136003)(396003)(366004)(39860400002)(346002)(376002)(199004)(189003)(36756003)(6506007)(51416003)(446003)(66946007)(76176011)(52116002)(50466002)(386003)(478600001)(6116002)(3846002)(14454004)(48376002)(5660300002)(966005)(6306002)(6666004)(14444005)(186003)(26005)(6512007)(4326008)(6436002)(2906002)(6486002)(99286004)(50226002)(2361001)(8676002)(81156014)(81166006)(8936002)(118296001)(2351001)(316002)(86362001)(6916009)(66066001)(16586007)(7736002)(305945005)(47776003)(25786009)(66556008)(66476007)(486006)(11346002)(54906003)(476003)(2616005);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR12MB3675;H:DM6PR12MB3163.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: txIQFjoiYcbg5t6kjjcIfAXUcUAMqfOIkIRdUFU/wn4e2tIa3BME+W4UECH/Uh59b7/s/3Ra+msnxWaxAPbhYPlOGnoJglx/rn7tVaHIk/ksi/dcBLMWTFGzfT+X05bQBp2hywfSnrSBCLPcIIbvs5swhUhmEOSoz1ALTcaAwh2UH02mGxDje/qxTmo+Ji1k61q8Zn9eOyEV4F6JJ1Xm+V8Aho3EH4yOzgT4NKEapoRbg29Nsr3pOArHQ0IyYDrj3BEhaRr348uKo+SyVByds9bV2/7Zc1RV956lWhBWfjqqq9BO38rJoKq0DadvF/h9ADSBi8k82AET5KZkQPxIMW0c2WHL23diUW22aQzH5DgnLhSJyUzDASBTzo03H+oEAlYTl1rqtpnjUqdRuTlxtHDVSzs1lz52cUj+PfOxD0RYnaktZbVrTy3oMUkyBRC8ihTqtQJwqShOLM61fgxurpDBZ2p+mHKqlG3JoI6dMHs= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4121a2b6-b9c2-474b-6195-08d76df5520d X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2019 20:07:50.8857 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lXDZ3EH1Z3DRL4Y3+Tw8tAQlui/RnHEFcossYWZfcNjjyPu/uAgcNaxj9hOsmoKOVJ3LESMT366K2oNCtUuwdw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3675 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index e5c36f37b96a..80e224b47fcd 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY Spare4; + GDT_ENTRY SysCode16; GDT_ENTRY LinearData64; GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 87fd6955f24b..6a80829be884 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate = { 0x0, }, // - // SPARE4_SEL + // SYS_CODE16_SEL // { - 0x0, // limit 15:0 + 0x0FFFF, // limit 15:0 0x0, // base 15:0 0x0, // base 23:16 - 0x0, // type - 0x0, // limit 19:16, flags + 0x09A, // present, ring 0, code, execute/read + 0x08F, // page-granular, 16-bit 0x0, // base 31:24 }, // diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24 %endif +; linear code segment descriptor +LINEAR_CODE16_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + GDT_END: -- 2.17.1