From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BB821202E53B2 for ; Tue, 12 Feb 2019 18:59:29 -0800 (PST) Received: by mail-pg1-x542.google.com with SMTP id s198so451011pgs.2 for ; Tue, 12 Feb 2019 18:59:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=GBcGSaPsuGicIug/SP8+EMlIagV7H7wal0UfUUevN9U=; b=YuJhqtk4Pe9VCKA8g2Bfr3QyQxYJcpdFWR3RdNoXCZ/RGqxoyuyYf9XpOmRkiCZlpO G47WaDoegUr5K+VOqefrdrKR/ruJxJG489hzjGYCAkmeV5dij5Ru4V50bsfik+koDDtS JvRm1QaXXwrXwqAMFcVXmjiKvV3WUpyUAgR487/GfIFuuN63KKlhUGRyP3TiQxAMGGjj IiroJQcj5ClPER5yopDSogd2nW7i0fwbsK0dhbp9wzN5xq9T3u5iEuO1ctHwYi2GYEKE KwtgigrlOsunILnJCALoRnosykz1kmg3q01vDW1U/xK0txcx2l1lKxuOwBjpao9QDNGV Ve1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=GBcGSaPsuGicIug/SP8+EMlIagV7H7wal0UfUUevN9U=; b=kG5iDRGnWsCSfKa0US+xYZE6HGjzKJ9qTSyipIb9YS+niFYZ/Ql1RzWBnmdSOVtuxQ cYpJMHLfPYZajwgF+gSfVrBwjRI9yBcz75LIzn1Mpm2d74MWRa/ac1IfnXeJ+XN3oNMQ kr0lHPy7siEMtOQ1FyJO5lCPn3XclLiEC0DGef/tliPLdtuiWE4KiD1xLzZn8VWpqokN DRPe8YcwCyOyBzTyyNT1vd7TJ9RiKONe/gf0R+b7CLt5vrBRThtZY+S8qKzKuAMNxtuk JvcnXePZPNy00i6xTKp0wlcQQcMxkylP+wrfiUbdRqp7AIW9v2UpKKH/qcmuFOE4phTh /llg== X-Gm-Message-State: AHQUAuaN65pYmakTpNvPIzh8VEHBo4MprUFTbzeiGw8WTHsyVlokqCbp BHHtyfi8vpysGe7+BxLEHQX5HA== X-Google-Smtp-Source: AHgI3IYDHSiEZVB5OtIMp9+lVfLUVLRZlOJJ46o9MW922YLAMjNIhYJi6K4WP7gZruHuGZOMFt9Prw== X-Received: by 2002:a63:5b1c:: with SMTP id p28mr6576444pgb.73.1550026769057; Tue, 12 Feb 2019 18:59:29 -0800 (PST) Received: from [10.58.0.74] ([64.64.108.254]) by smtp.gmail.com with ESMTPSA id z186sm19805607pfz.119.2019.02.12.18.59.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 18:59:28 -0800 (PST) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, zhangfeng56@huawei.com References: <20190201133436.10500-1-ming.huang@linaro.org> <20190201133436.10500-10-ming.huang@linaro.org> <20190211185140.6vn7swtqtiencdak@bivouac.eciton.net> From: Ming Huang Message-ID: <71d90497-0095-5709-9938-3ac31212bb8d@linaro.org> Date: Wed, 13 Feb 2019 10:59:17 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20190211185140.6vn7swtqtiencdak@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v1 09/16] Hisilicon/D06: Add PCI_OSC_SUPPORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Feb 2019 02:59:29 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 2/12/2019 2:51 AM, Leif Lindholm wrote: > On Fri, Feb 01, 2019 at 09:34:29PM +0800, Ming Huang wrote: >> Add PCI_OSC_SUPPORT for remaining host bridges to remove fail >> output in kernel: >> [ 103.478893] acpi PNP0A08:01: _OSC failed (AE_NOT_FOUND); >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl | 64 ++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> index 4d9d9d95be68..86d8728b82f2 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl >> @@ -17,6 +17,50 @@ >> **/ >> >> //#include "ArmPlatform.h" >> + >> +/* >> + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 >> +*/ >> +#define PCI_OSC_SUPPORT() \ > > PCI0 and PCI6 already have _OSC entries. > This macro ends up being used for 1-5 and 7-B. > So calling it PCI_OSC_SUPPORT seems somewhat misleading. > > Then again, there is a lot of similarities between this macro and the > existing entries. Could the same macro be used for 0 and 6? Or could > the macro be split up into multiple parts and reused? When I make this patch, I try to rewrite PCI0/6 with the same macro, but the macro don't support parameter. For spliting up multiple parts, if modify something in future, the parts need to split up to smaller parts. So, if need to rewrite PCI0/6 with macro, is it applicable to add another macro PCI_OSC_SUPPORT_HOTPLUG? Thanks > > / > Leif > >> + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ >> + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ >> + Method(_OSC,4) { \ >> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ >> + /* Create DWord-adressable fields from the Capabilities Buffer */ \ >> + CreateDWordField(Arg3,0,CDW1) \ >> + CreateDWordField(Arg3,4,CDW2) \ >> + CreateDWordField(Arg3,8,CDW3) \ >> + /* Save Capabilities DWord2 & 3 */ \ >> + Store(CDW2,SUPP) \ >> + Store(CDW3,CTRL) \ >> + /* Only allow native hot plug control if OS supports: */ \ >> + /* ASPM */ \ >> + /* Clock PM */ \ >> + /* MSI/MSI-X */ \ >> + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ >> + And(CTRL,0x1E,CTRL) \ >> + }\ >> + \ >> + /* Do not allow native PME, AER */ \ >> + /* Never allow SHPC (no SHPC controller in this system)*/ \ >> + And(CTRL,0x10,CTRL) \ >> + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ >> + Or(CDW1,0x08,CDW1) \ >> + } \ >> + \ >> + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ >> + Or(CDW1,0x10,CDW1) \ >> + } \ >> + \ >> + /* Update DWORD3 in the buffer */ \ >> + Store(CTRL,CDW3) \ >> + Return(Arg3) \ >> + } Else { \ >> + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ >> + Return(Arg3) \ >> + } \ >> + } // End _OSC >> + >> Scope(_SB) >> { >> Device (PCI0) >> @@ -270,6 +314,8 @@ Device (PCI1) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -333,6 +379,8 @@ Device (PCI2) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -382,6 +430,8 @@ Device (PCI3) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -431,6 +481,8 @@ Device (PCI4) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0x0F) >> @@ -505,6 +557,8 @@ Device (PCI5) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -1002,6 +1056,8 @@ Device (PCI7) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -1066,6 +1122,8 @@ Device (PCI8) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -1115,6 +1173,8 @@ Device (PCI9) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> @@ -1164,6 +1224,8 @@ Device (PCIA) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0x0F) >> @@ -1238,6 +1300,8 @@ Device (PCIB) >> Return (RBUF) >> } // Method(_CRS), this method return RBUF! >> >> + PCI_OSC_SUPPORT () >> + >> Method (_STA, 0x0, NotSerialized) >> { >> Return (0xf) >> -- >> 2.9.5 >>