From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 8DA58740039 for ; Wed, 31 Jan 2024 02:15:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=k4Rut5V77iRbd76WeUKhhEavEi4ZevJEqvgoxy++4M8=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1706667333; v=1; b=VjokR1HGHzjyjPRuSrIvzM8GHFkxrTaZyIY9uCTe3olGInweMhhdznMlper8F5FlA02dKNPI j3mJ9EyBi8eptiW1UMUpPW0gpyf9W2idSwky+LTDuZ78nKHbJ+WWur3ef8S20Wi3MvHraTY2bUV y/9xWdO31L+ZmavFDcVVSPks= X-Received: by 127.0.0.2 with SMTP id 9ol8YY7687511xX14jVPASwt; Tue, 30 Jan 2024 18:15:33 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by mx.groups.io with SMTP id smtpd.web11.5417.1706667332284055196 for ; Tue, 30 Jan 2024 18:15:32 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="16848388" X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="16848388" X-Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2024 18:15:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,231,1701158400"; d="scan'208";a="30082671" X-Received: from tedkuo1-desk1.gar.corp.intel.com ([10.225.76.14]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2024 18:15:29 -0800 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Eric Dong , Ashraf Ali S , Chinni B Duggapu , Liming Gao Subject: [edk2-devel][edk2-platforms][PATCH v6] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Date: Wed, 31 Jan 2024 10:14:55 +0800 Message-Id: <72fdc320f044cc7576e19ec3e3463450eadc2a33.1706667131.git.ted.kuo@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 6rKHtU6XDGRPtHcwnsXr4RGlx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=VjokR1HG; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io https://bugzilla.tianocore.org/show_bug.cgi?id=3D4623 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64. 2.Made changes in common files to support both IA32 and X64. 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP. - PcdFspWrapperResetVectorInFsp - PcdFspWrapperBfvforResetVectorInFsp - PcdFsptUpdHeaderRevision - PcdFsptArchUpdRevision Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Eric Dong Cc: Ashraf Ali S Cc: Chinni B Duggapu Cc: Liming Gao Signed-off-by: Ted Kuo --- .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++- .../Ia32/SecEntry.nasm | 4 +- .../SecFspWrapperPlatformSecLib.inf | 12 +- .../SecGetPerformance.c | 11 +- .../SecPlatformInformation.c | 8 +- .../SecRamInitData.c | 77 +++++-- .../X64/PeiCoreEntry.nasm | 207 ++++++++++++++++++ .../X64/SecEntry.nasm | 199 +++++++++++++++++ .../X64/Stack.nasm | 72 ++++++ .../Ia32 =3D> Include}/Fsp.h | 6 +- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 23 +- 11 files changed, 612 insertions(+), 32 deletions(-) create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/PeiCoreEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/SecEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/Stack.nasm rename Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlat= formSecLib/Ia32 =3D> Include}/Fsp.h (79%) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FsptCoreUpd.h b/Platform/Intel/MinPlatformPkg/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/FsptCoreUpd.h index 7c0f605b92..24c18f25b8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FsptCoreUpd.h +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FsptCoreUpd.h @@ -1,6 +1,6 @@ /** @file=0D =0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D #pragma pack(1)=0D =0D +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <=3D 1=0D /** Fsp T Core UPD=0D **/=0D typedef struct {=0D @@ -34,6 +35,28 @@ typedef struct { **/=0D UINT8 Reserved[16];=0D } FSPT_CORE_UPD;=0D +#else=0D +/** Fsp T Core UPD=0D +**/=0D +typedef struct {=0D +=0D +/** Offset 0x0040=0D +**/=0D + EFI_PHYSICAL_ADDRESS MicrocodeRegionBase;=0D +=0D +/** Offset 0x0048=0D +**/=0D + UINT64 MicrocodeRegionSize;=0D +=0D +/** Offset 0x0050=0D +**/=0D + EFI_PHYSICAL_ADDRESS CodeRegionBase;=0D +=0D +/** Offset 0x0058=0D +**/=0D + UINT64 CodeRegionSize;=0D +} FSPT_CORE_UPD;=0D +#endif=0D =0D #pragma pack()=0D =0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrappe= r/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm index 7f6d771e41..0b3f343991 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/SecEntry.nasm +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/SecEntry.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= -----=0D ;=0D -; Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ; Module Name:=0D ;=0D @@ -13,7 +13,7 @@ ;=0D ;-------------------------------------------------------------------------= -----=0D =0D -#include "Fsp.h"=0D +#include =0D =0D SECTION .text=0D =0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec= Lib.inf index 2e0d67eae4..e85243c6e3 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file=0D # Provide FSP wrapper platform sec related function.=0D #=0D -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -47,7 +47,11 @@ Ia32/SecEntry.nasm=0D Ia32/PeiCoreEntry.nasm=0D Ia32/Stack.nasm=0D - Ia32/Fsp.h=0D +=0D +[Sources.X64]=0D + X64/SecEntry.nasm=0D + X64/PeiCoreEntry.nasm=0D + X64/Stack.nasm=0D =0D ##########################################################################= ######=0D #=0D @@ -96,3 +100,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES=0D gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision ## C= ONSUMES=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecGetPerformance.c b/Platform/Intel/MinPlatformPkg/FspWrapp= er/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c index ac2deeabec..1699bd9710 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecGetPerformance.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecGetPerformance.c @@ -1,7 +1,7 @@ /** @file=0D Sample to provide SecGetPerformance function.=0D =0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -58,6 +58,7 @@ SecGetPerformance ( if (EFI_ERROR (Status)) {=0D return EFI_NOT_FOUND;=0D }=0D +=0D //=0D // |--------------| <- TopOfTemporaryRam - BL=0D // | List Ptr |=0D @@ -77,12 +78,12 @@ SecGetPerformance ( // | TSC[31:00] |=0D // |--------------|=0D //=0D - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);=0D - TopOfTemporaryRam -=3D sizeof (UINT32) * 2;=0D - Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));= =0D + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);=0D + TopOfTemporaryRam -=3D sizeof(UINTN) * 2;=0D + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (U= INT32));=0D Size =3D Count * sizeof (UINT32);=0D =0D - Ticker =3D *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - siz= eof (UINT32) * 2);=0D + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze - sizeof (UINT64));=0D Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker);=0D =0D return EFI_SUCCESS;=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecPlatformInformation.c b/Platform/Intel/MinPlatformPkg/Fsp= Wrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c index 24d55ed838..4cbde95c2d 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecPlatformInformation.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecPlatformInformation.c @@ -1,7 +1,7 @@ /** @file=0D Provide SecPlatformInformation function.=0D =0D -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -59,9 +59,9 @@ SecPlatformInformation ( // This routine copies the BIST information to the buffer pointed by=0D // PlatformInformationRecord for output.=0D //=0D - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);=0D - TopOfTemporaryRam -=3D sizeof (UINT32) * 2;=0D - Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)))= ;=0D + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN);=0D + TopOfTemporaryRam -=3D sizeof (UINTN) * 2;=0D + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (U= INT32)));=0D Size =3D Count * sizeof (IA32_HANDOFF_STATUS);=0D =0D if ((*StructureSize) < (UINT64) Size) {=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/= Library/SecFspWrapperPlatformSecLib/SecRamInitData.c index 355d1e6509..f91c4c1d19 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file=0D Provide TempRamInitParams data.=0D =0D -Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -10,27 +10,76 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include "FsptCoreUpd.h"=0D =0D +#if defined (MDE_CPU_IA32) && FixedPcdGetBool (PcdFspWrapperResetVectorInF= sp) =3D=3D 1=0D +#error "PcdFspWrapperResetVectorInFsp =3D=3D TRUE only supported for X64 b= uilds"=0D +#endif=0D +=0D typedef struct {=0D FSP_UPD_HEADER FspUpdHeader;=0D +#if FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 1=0D + FSPT_ARCH_UPD FsptArchUpd;=0D +#elif FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2=0D + FSPT_ARCH2_UPD FsptArchUpd;=0D +#endif=0D FSPT_CORE_UPD FsptCoreUpd;=0D -} FSPT_UPD_CORE_DATA;=0D + UINT16 UpdTerminator;=0D +} FSPT_UPD_DATA;=0D =0D -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D = {=0D +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_DATA FsptUpdDataPtr =3D {=0D + {=0D + 0x4450555F54505346, // FSP-T= UPD Header Signature - FSPT_UPD=0D + FixedPcdGet8 (PcdFsptUpdHeaderRevision), // FSP-T= UPD Header Revision=0D + { // Reser= ved[23]=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00=0D + }=0D + },=0D +#if FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 1=0D + {=0D + 0x01, // FSP-T= ARCH UPD Revision=0D + { // Reser= ved[3]=0D + 0x00, 0x00, 0x00=0D + },=0D + 0x00000020, // Lengt= h of FSP-T ARCH UPD=0D + 0, // FspDe= bugHandler=0D + { // Reser= ved1[20]=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + }=0D + },=0D +#elif FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2=0D {=0D - 0x4450555F54505346,=0D - 0x00,=0D - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + 0x02, // FSP-T= ARCH2 UPD Revision=0D + { // Reser= ved[3]=0D + 0x00, 0x00, 0x00=0D + },=0D + 0x00000020, // Lengt= h of FSP-T ARCH2 UPD=0D + 0, // FspDe= bugHandler=0D + { // Reser= ved1[16]=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D }=0D },=0D +#endif=0D +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <=3D 1=0D {=0D - FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D - FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D - 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D - FixedPcdGet32 (PcdFlashCodeCacheSize),=0D - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionBase=0D + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionSize=0D + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegion= Size > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D + FixedPcdGet32 (PcdFlashCodeCacheSize), = // CodeRegionSize=0D + { = // Reserved[16]=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D }=0D - }=0D + },=0D +#else=0D + {=0D + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionBase=0D + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionSize=0D + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegion= Size > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D + FixedPcdGet32 (PcdFlashCodeCacheSize) = // CodeRegionSize=0D + },=0D +#endif=0D + 0x55AA=0D };=0D -=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/PeiCoreEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWra= pper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm new file mode 100644 index 0000000000..08933c6d37 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/PeiCoreEntry.nasm @@ -0,0 +1,207 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2024, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +; Module Name:=0D +;=0D +; PeiCoreEntry.nasm=0D +;=0D +; Abstract:=0D +;=0D +; Find and call SecStartup=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +SECTION .text=0D +=0D +extern ASM_PFX(SecStartup)=0D +extern ASM_PFX(PlatformInit)=0D +extern ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))=0D +=0D +;-------------------------------------------------------------------------= ----=0D +; Macro: PUSHA_64=0D +;=0D +; Description: Saves all registers on stack=0D +;=0D +; Input: None=0D +;=0D +; Output: None=0D +;-------------------------------------------------------------------------= ----=0D +%macro PUSHA_64 0=0D + push r8=0D + push r9=0D + push r10=0D + push r11=0D + push r12=0D + push r13=0D + push r14=0D + push r15=0D + push rax=0D + push rcx=0D + push rdx=0D + push rbx=0D + push rsp=0D + push rbp=0D + push rsi=0D + push rdi=0D +%endmacro=0D +=0D +;-------------------------------------------------------------------------= ----=0D +; Macro: POPA_64=0D +;=0D +; Description: Restores all registers from stack=0D +;=0D +; Input: None=0D +;=0D +; Output: None=0D +;-------------------------------------------------------------------------= ----=0D +%macro POPA_64 0=0D + pop rdi=0D + pop rsi=0D + pop rbp=0D + pop rsp=0D + pop rbx=0D + pop rdx=0D + pop rcx=0D + pop rax=0D + pop r15=0D + pop r14=0D + pop r13=0D + pop r12=0D + pop r11=0D + pop r10=0D + pop r9=0D + pop r8=0D +%endmacro=0D +=0D +global ASM_PFX(CallPeiCoreEntryPoint)=0D +ASM_PFX(CallPeiCoreEntryPoint):=0D + ;=0D + ; Per X64 calling convention, make sure RSP is 16-byte aligned.=0D + ;=0D + mov rax, rsp=0D + and rax, 0fh=0D + sub rsp, rax=0D +=0D + ;=0D + ; Platform init=0D + ;=0D + PUSHA_64=0D + sub rsp, 20h=0D + call ASM_PFX(PlatformInit)=0D + add rsp, 20h=0D + POPA_64=0D +=0D + ;=0D + ; Set stack top pointer=0D + ;=0D + mov rsp, r8=0D +=0D + ;=0D + ; Push the hob list pointer=0D + ;=0D + push rcx=0D +=0D + ;=0D + ; RBP holds start of BFV passed from Vtf0. Save it to r10.=0D + ;=0D + mov r10, rbp=0D +=0D + ;=0D + ; Save the value=0D + ; RDX: start of range=0D + ; r8: end of range=0D + ;=0D + mov rbp, rsp=0D + push rdx=0D + push r8=0D + mov r14, rdx=0D + mov r15, r8=0D +=0D + ;=0D + ; Push processor count to stack first, then BIST status (AP then BSP)=0D + ;=0D + mov eax, 1=0D + cpuid=0D + shr ebx, 16=0D + and ebx, 0000000FFh=0D + cmp bl, 1=0D + jae PushProcessorCount=0D +=0D + ;=0D + ; Some processors report 0 logical processors. Effectively 0 =3D 1.=0D + ; So we fix up the processor count=0D + ;=0D + inc ebx=0D +=0D +PushProcessorCount:=0D + sub rsp, 4=0D + mov rdi, rsp=0D + mov DWORD [rdi], ebx=0D +=0D + ;=0D + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST=0D + ; for all processor threads=0D + ;=0D + xor ecx, ecx=0D + mov cl, bl=0D +PushBist:=0D + sub rsp, 4=0D + mov rdi, rsp=0D + movd eax, mm0=0D + mov DWORD [rdi], eax=0D + loop PushBist=0D +=0D + ;=0D + ; FSP saves the timestamp of the beginning of firmware execution in mm5.= =0D + ; Get the timestamp from mm5 and then push to stack.=0D + ;=0D + movq rax, mm5=0D + push rax=0D +=0D + ;=0D + ; Per X64 calling convention, make sure RSP is 16-byte aligned.=0D + ;=0D + mov rax, rsp=0D + and rax, 0fh=0D + sub rsp, rax=0D +=0D + ;=0D + ; Pass entry point of the PEI core=0D + ;=0D + mov rdi, 0FFFFFFE0h=0D + mov edi, DWORD [rdi]=0D + mov r9, rdi=0D +=0D + ;=0D + ; Pass BFV into the PEI Core=0D + ;=0D +#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 1=0D + ;=0D + ; Reset Vector and initial SEC core (to initialize Temp Ram) is part of = FSP-O.=0D + ; Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actu= al=0D + ; SEC core that launches PEI is part of another FV. We need to pass that= FV=0D + ; as BFV to PEI core.=0D + ;=0D + mov r8, ASM_PFX (PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))=0D + mov rcx, QWORD[r8]=0D + mov r8, rcx=0D +#else=0D + mov r8, r10=0D +#endif=0D +=0D + ;=0D + ; Pass stack size into the PEI Core=0D + ;=0D + mov rcx, r15 ; Start of TempRam=0D + mov rdx, r14 ; End of TempRam=0D +=0D + sub rcx, rdx ; Size of TempRam=0D +=0D + ;=0D + ; Pass Control into the PEI Core=0D + ;=0D + sub rsp, 20h=0D + call ASM_PFX(SecStartup)=0D +=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper= /Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm new file mode 100644 index 0000000000..2618860366 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/SecEntry.nasm @@ -0,0 +1,199 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2024, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +; Module Name:=0D +;=0D +; SecEntry.nasm=0D +;=0D +; Abstract:=0D +;=0D +; This is the code that passes control to PEI core.=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +#include =0D +=0D +SECTION .text=0D +=0D +extern ASM_PFX(CallPeiCoreEntryPoint)=0D +extern ASM_PFX(FsptUpdDataPtr)=0D +; Pcds=0D +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))=0D +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))=0D +=0D +;-------------------------------------------------------------------------= ---=0D +;=0D +; Procedure: _ModuleEntryPoint=0D +;=0D +; Input: None=0D +;=0D +; Output: None=0D +;=0D +; Destroys: Assume all registers=0D +;=0D +; Description:=0D +;=0D +; Call TempRamInit API from FSP binary if reset vector in FSP is not supp= roted.=0D +; After TempRamInit done, pass control to PEI core.=0D +;=0D +; Return: None=0D +;=0D +; MMX Usage:=0D +; MM0 =3D BIST State=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +=0D +BITS 64=0D +align 16=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D +#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 1=0D + push rax=0D + mov rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include Te= mpRamInitParams in SecCore for FSP-O.=0D + pop rax=0D +#else=0D + fninit ; clear any pending Floating point= exceptions=0D + ;=0D + ; Store the BIST value in mm0=0D + ;=0D + movd mm0, eax=0D + cli=0D +=0D + ;=0D + ; Trigger warm reset if PCIEBAR register is not in reset/default value s= tate=0D + ;=0D + mov eax, 80000060h ; PCIEX_BAR_REG B0:D0:F0:R60=0D + mov dx, 0CF8h=0D + out dx, eax=0D + mov dx, 0CFCh=0D + in eax, dx=0D + cmp eax, 0=0D + jz NotWarmStart=0D +=0D + ;=0D + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs= are restored to their defaults=0D + ;=0D + mov dx, 0CF9h=0D + mov al, 06h=0D + out dx, al=0D + jmp $=0D +=0D +NotWarmStart:=0D +=0D + ; Find the fsp info header=0D + mov rax, ASM_PFX(PcdGet32 (PcdFsptBaseAddress))=0D + mov edi, [eax]=0D +=0D + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]=0D + cmp eax, FVH_SIGINATURE_VALID_VALUE=0D + jnz FspHeaderNotFound=0D +=0D + xor eax, eax=0D + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]=0D + cmp ax, 0=0D + jnz FspFvExtHeaderExist=0D +=0D + xor eax, eax=0D + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header= =0D + add edi, eax=0D + jmp FspCheckFfsHeader=0D +=0D +FspFvExtHeaderExist:=0D + add edi, eax=0D + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv He= ader=0D + add edi, eax=0D +=0D + ; Round up to 8 byte alignment=0D + mov eax, edi=0D + and al, 07h=0D + jz FspCheckFfsHeader=0D +=0D + and edi, 0FFFFFFF8h=0D + add edi, 08h=0D +=0D +FspCheckFfsHeader:=0D + ; Check the ffs guid=0D + mov eax, dword [edi]=0D + cmp eax, FSP_HEADER_GUID_DWORD1=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 4]=0D + cmp eax, FSP_HEADER_GUID_DWORD2=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 8]=0D + cmp eax, FSP_HEADER_GUID_DWORD3=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 0Ch]=0D + cmp eax, FSP_HEADER_GUID_DWORD4=0D + jnz FspHeaderNotFound=0D +=0D + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header=0D +=0D + ; Check the section type as raw section=0D + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]=0D + cmp al, 019h=0D + jnz FspHeaderNotFound=0D +=0D + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header=0D + jmp FspHeaderFound=0D +=0D +FspHeaderNotFound:=0D + jmp $=0D +=0D +FspHeaderFound:=0D + ; Get the fsp TempRamInit Api address=0D + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]=0D + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]=0D +=0D + ; Setup the hardcode stack=0D + mov rsp, TempRamInitStack ; move return address to rsp=0D + mov rcx, ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams=0D +=0D + ; Call the fsp TempRamInit Api=0D + jmp rax=0D +=0D +TempRamInitDone:=0D + mov rbx, 0800000000000000Eh=0D + cmp rax, rbx ; Check if EFI_NOT_FOUND returned. Error= code for Microcode Update not found.=0D + je CallSecFspInit ; If microcode not found, don't hang, bu= t continue.=0D +=0D + test rax, rax ; Check if EFI_SUCCESS returned.=0D + jnz FspApiFailed=0D +=0D +CallSecFspInit:=0D +#endif=0D +=0D + ; RDX: start of range=0D + ; R8: end of range=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1=0D + push rax=0D + mov rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))=0D + sub edx, dword [rax] ; TemporaryRam for FSP=0D + pop rax=0D +#endif=0D +=0D + mov r8, rdx=0D + mov rdx, rcx=0D + xor ecx, ecx ; zero - no Hob List Yet=0D + mov rsp, r8=0D +=0D + ;=0D + ; Per X64 calling convention, make sure RSP is 16-byte aligned.=0D + ;=0D + mov rax, rsp=0D + and rax, 0fh=0D + sub rsp, rax=0D +=0D + call ASM_PFX(CallPeiCoreEntryPoint)=0D +=0D +FspApiFailed:=0D + jmp $=0D +=0D +#if FixedPcdGetBool (PcdFspWrapperResetVectorInFsp) =3D=3D 0=0D +align 10h=0D +TempRamInitStack:=0D + DQ TempRamInitDone=0D +#endif=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/Stack.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Li= brary/SecFspWrapperPlatformSecLib/X64/Stack.nasm new file mode 100644 index 0000000000..21010bf4ef --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2024, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +; Abstract:=0D +;=0D +; Switch the stack from temporary memory to permanent memory.=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D + SECTION .text=0D +=0D +;-------------------------------------------------------------------------= -----=0D +; VOID=0D +; EFIAPI=0D +; SecSwitchStack (=0D +; UINT32 TemporaryMemoryBase,=0D +; UINT32 PermanentMemoryBase=0D +; );=0D +;-------------------------------------------------------------------------= -----=0D +global ASM_PFX(SecSwitchStack)=0D +ASM_PFX(SecSwitchStack):=0D + ;=0D + ; Save four register: rax, rbx, rcx, rdx=0D + ;=0D + push rax=0D + push rbx=0D + push rcx=0D + push rdx=0D +=0D + ;=0D + ; !!CAUTION!! this function address's is pushed into stack after=0D + ; migration of whole temporary memory, so need save it to permanent=0D + ; memory at first!=0D + ;=0D +=0D + mov rbx, rcx ; Save the first parameter=0D + mov rcx, rdx ; Save the second parameter=0D +=0D + ;=0D + ; Save this function's return address into permanent memory at first.= =0D + ; Then, Fixup the esp point to permanent memory=0D + ;=0D + mov rax, rsp=0D + sub rax, rbx=0D + add rax, rcx=0D + mov rdx, qword [rsp] ; copy pushed register's value to perma= nent memory=0D + mov qword [rax], rdx=0D + mov rdx, qword [rsp + 8]=0D + mov qword [rax + 8], rdx=0D + mov rdx, qword [rsp + 16]=0D + mov qword [rax + 16], rdx=0D + mov rdx, qword [rsp + 24]=0D + mov qword [rax + 24], rdx=0D + mov rdx, qword [rsp + 32] ; Update this function's return address= into permanent memory=0D + mov qword [rax + 32], rdx=0D + mov rsp, rax ; From now, rsp is pointed to permanent= memory=0D +=0D + ;=0D + ; Fixup the rbp point to permanent memory=0D + ;=0D + mov rax, rbp=0D + sub rax, rbx=0D + add rax, rcx=0D + mov rbp, rax ; From now, rbp is pointed to permanent= memory=0D +=0D + pop rdx=0D + pop rcx=0D + pop rbx=0D + pop rax=0D + ret=0D +=0D diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h similarity index 79% rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/Fsp.h rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h index 9f6cdcf476..319e1e3372 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/Fsp.h +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h @@ -1,7 +1,7 @@ /** @file=0D Fsp related definitions=0D =0D -Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //=0D // Fsp Header=0D //=0D -#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C=0D -#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30=0D +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C=0D +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30=0D =0D #endif=0D diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index a14c6b2db5..74e1bce87f 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -6,7 +6,7 @@ # INF files to generate AutoGen.c and AutoGen.h files=0D # for the build infrastructure.=0D #=0D -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
=0D # Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -393,6 +393,27 @@ #=0D gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLE= AN|0xF00000A8=0D =0D + ## Reset Vector in FSP=0D + # FALSE: Reset Vector is in FSP Wrapper=0D + # TRUE: Reset Vector is in FSP - This is only supported in X64=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|BOOLEA= N|0xF00000A9=0D +=0D + ## BFV Location for Reset Vector in FSP=0D + # The default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0= 000.=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x0000= 0000FFFF0000|UINT64|0xF00000AA=0D +=0D + ## FSP-T UPD Header Revision=0D + # The default of FSP-T UPD Header Revision is 0.=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0xF0000= 0AB=0D +=0D + ## FSP-T ARCH UPD Revision=0D + # The default of FSP-T ARCH UPD Revision is 0.=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF00000A= C=0D +=0D [PcdsFeatureFlag]=0D =0D gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0= xF00000A1=0D --=20 2.40.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114843): https://edk2.groups.io/g/devel/message/114843 Mute This Topic: https://groups.io/mt/104067932/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-