From: "Ni, Ruiyu" <ruiyu.ni@intel.com>
To: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
"Gao, Liming" <liming.gao@intel.com>,
"afish@apple.com" <afish@apple.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>,
"mw@semihalf.com" <mw@semihalf.com>,
"Tian, Feng" <feng.tian@intel.com>
Subject: Re: [PATCH v4 3/5] MdeModulePkg: implement generic PCI I/O driver for non-discoverable devices
Date: Fri, 2 Dec 2016 12:54:45 +0000 [thread overview]
Message-ID: <734D49CCEBEEF84792F5B80ED585239D58E926A5@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <20161130140655.GG27069@bivouac.eciton.net>
Regards,
Ray
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Wednesday, November 30, 2016 10:07 PM
>To: Ni, Ruiyu <ruiyu.ni@intel.com>
>Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>; edk2-devel@lists.01.org; Gao, Liming <liming.gao@intel.com>;
>afish@apple.com; Kinney, Michael D <michael.d.kinney@intel.com>; mw@semihalf.com; Tian, Feng <feng.tian@intel.com>
>Subject: Re: [PATCH v4 3/5] MdeModulePkg: implement generic PCI I/O driver for non-discoverable devices
>
>Hi Ray,
>
>Ard is on holiday this week, and mostly managing to stay off the
>email...
>
>Anyway, I could really use this support in order to bring the Marvell
>Armada 70x0 support (worked on by the Semihalf guys) into
>OpenPlatformPkg, so I will pick this up while he is away - at least
>parts 1-3.
>
>4/5 is required for 5/5, so I will not be looking to push the final
>one myself.
>
>Would you OK with pushing just 1-3 once we get this one resolved?
>
>On Mon, Nov 28, 2016 at 01:56:21AM +0000, Ni, Ruiyu wrote:
>> > diff --git
>> > a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > PciDeviceIo.c
>> > b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > PciDeviceIo.c
>> > new file mode 100644
>> > index 000000000000..fd59267a8d66
>> > --- /dev/null
>> > +++
>> > b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > Pc
>> > +++ iDeviceIo.c
>> > @@ -0,0 +1,797 @@
>...
>> > +VOID
>> > +InitializePciIoProtocol (
>> > + NON_DISCOVERABLE_PCI_DEVICE *Dev
>> > + )
>> > +{
>> > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
>> > + INTN Idx;
>> > +
>> > + InitializeListHead (&Dev->UncachedAllocationList);
>
>The above line has crept in here, but belongs to 4/5 (causes
>compilation error). I will fix that and resend - is it OK if I resend
>this patch only?
>
>> > + // Iterate over the resources to populate the virtual BARs
>> > + //
>> > + Idx = Dev->BarOffset;
>> > + for (Desc = Dev->Device->Resources, Dev->BarCount = 0;
>> > + Desc->Desc != ACPI_END_TAG_DESCRIPTOR;
>> > + Desc = (VOID *)((UINT8 *)Desc + Desc->Len + 3)) {
>> > +
>> > + ASSERT (Desc->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR);
>> > + ASSERT (Desc->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM);
>> > +
>> > + if (Idx >= PCI_MAX_BARS ||
>> > + (Idx == PCI_MAX_BARS - 1 && Desc->AddrSpaceGranularity == 64)) {
>> > + DEBUG ((DEBUG_ERROR,
>> > + "%a: resource count exceeds number of emulated BARs\n",
>> > + __FUNCTION__));
>> > + ASSERT (FALSE);
>> > + break;
>> > + }
>> > +
>> > + Dev->ConfigSpace.Device.Bar[Idx] = (UINT32)Desc->AddrRangeMin;
>> > + Dev->BarCount++;
>> > +
>> > + if (Desc->AddrSpaceGranularity == 64) {
>> > + Dev->ConfigSpace.Device.Bar[Idx] |= 0x4;
>> > + Dev->ConfigSpace.Device.Bar[++Idx] = (UINT32)(Desc->AddrRangeMin >> 32);
>>
>> 1. You need to use RShiftU64 otherwise the above code will break the
>> build process in 32bit.
>
>I don't understand how that could cause breakage (and experiments with
>IA32 and ARM fail to reproduce it with GCC).
>
>- Bar[x] is an array of UINT32
>- Desc->AddrRangeMin is UINT64
>- The result of (Desc->AddrRangeMin >> 32) is explicitly cast to
> UINT32 (the type of Bar[x]).
>
>Is the problem related to the shift value being signed?
>Or does some other compiler refuse to cast a UINT64 to a UINT32?
Desc->AddrRangeMin is UINT64. My experience tells me that
LShiftU64 or RShiftU64 should be used for shifting operation
on UINT64.
I guess the GCC might cleverly recognizes the ">>32" actually
picks up the high-32 bits so in 32bit environment, it just uses
value of the register which stores the high-32 bits.
Can you check the assembly code GCC generates?
or simply can you change ">>32" to ">>31" or ">>33" to see
what happens?
>
>Regards,
>
>Leif
>
>> > + }
>> > + }
>> > +}
>> > diff --git
>> > a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > PciDeviceIo.h
>> > b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > PciDeviceIo.h
>> > new file mode 100644
>> > index 000000000000..bc0a3d3258f9
>> > --- /dev/null
>> > +++
>> > b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverable
>> > Pc
>> > +++ iDeviceIo.h
>> > @@ -0,0 +1,84 @@
>> > +/** @file
>> > +
>> > + Copyright (C) 2016, Linaro Ltd. All rights reserved.<BR>
>> > +
>> > + This program and the accompanying materials are licensed and made
>> > + available under the terms and conditions of the BSD License which
>> > + accompanies this distribution. The full text of the license may be
>> > + found at http://opensource.org/licenses/bsd-license.php
>> > +
>> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> > BASIS,
>> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> > EXPRESS OR IMPLIED.
>> > +
>> > +**/
>> > +
>> > +#ifndef __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
>> > +#define __NON_DISCOVERABLE_PCI_DEVICE_IO_H__
>> > +
>> > +#include <Library/BaseMemoryLib.h>
>> > +#include <Library/DebugLib.h>
>> > +#include <Library/MemoryAllocationLib.h> #include
>> > +<Library/UefiBootServicesTableLib.h>
>> > +#include <Library/UefiLib.h>
>> > +
>> > +#include <IndustryStandard/Pci.h>
>> > +
>> > +#include <Protocol/ComponentName.h>
>> > +#include <Protocol/NonDiscoverableDevice.h>
>> > +#include <Protocol/PciIo.h>
>> > +
>> > +#define NON_DISCOVERABLE_PCI_DEVICE_SIG SIGNATURE_32 ('P', 'P', 'I',
>> > +'D')
>> > +
>> > +#define NON_DISCOVERABLE_PCI_DEVICE_FROM_PCI_IO(PciIoPointer) \
>> > + CR (PciIoPointer, NON_DISCOVERABLE_PCI_DEVICE, PciIo, \
>> > + NON_DISCOVERABLE_PCI_DEVICE_SIG)
>> > +
>> > +#define PCI_ID_VENDOR_UNKNOWN 0xffff
>> > +#define PCI_ID_DEVICE_DONTCARE 0x0000
>> > +
>> > +#define PCI_MAX_BARS 6
>> > +
>> > +typedef struct {
>> > + UINT32 Signature;
>> > + //
>> > + // The bound non-discoverable device protocol instance
>> > + //
>> > + NON_DISCOVERABLE_DEVICE *Device;
>> > + //
>> > + // The exposed PCI I/O protocol instance.
>> > + //
>> > + EFI_PCI_IO_PROTOCOL PciIo;
>> > + //
>> > + // The emulated PCI config space of the device. Only the minimally
>> > +required
>> > + // items are assigned.
>> > + //
>> > + PCI_TYPE00 ConfigSpace;
>> > + //
>> > + // The first virtual BAR to assign based on the resources described
>> > + // by the non-discoverable device.
>> > + //
>> > + UINT32 BarOffset;
>> > + //
>> > + // The number of virtual BARs we expose based on the number of
>> > + // resources
>> > + //
>> > + UINT32 BarCount;
>> > + //
>> > + // The PCI I/O attributes for this device
>> > + //
>> > + UINT64 Attributes;
>> > + //
>> > + // Whether this device has been enabled
>> > + //
>> > + BOOLEAN Enabled;
>> > +} NON_DISCOVERABLE_PCI_DEVICE;
>> > +
>> > +VOID
>> > +InitializePciIoProtocol (
>> > + NON_DISCOVERABLE_PCI_DEVICE *Device
>> > + );
>> > +
>> > +extern EFI_COMPONENT_NAME_PROTOCOL gComponentName; extern
>> > +EFI_COMPONENT_NAME2_PROTOCOL gComponentName2;
>> > +
>> > +#endif
>> > diff --git a/MdeModulePkg/MdeModulePkg.dsc
>> > b/MdeModulePkg/MdeModulePkg.dsc index 20e5e8c78be0..5dd30556cb3c
>> > 100644
>> > --- a/MdeModulePkg/MdeModulePkg.dsc
>> > +++ b/MdeModulePkg/MdeModulePkg.dsc
>> > @@ -265,6 +265,7 @@ [Components]
>> > MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
>> > MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
>> > MdeModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
>> > +
>> > +
>> > MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePci
>> > Dev
>> > + iceDxe.inf
>> >
>> > MdeModulePkg/Core/Dxe/DxeMain.inf {
>> > <LibraryClasses>
>> > --
>> > 2.7.4
>>
next prev parent reply other threads:[~2016-12-02 12:54 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-25 15:42 [PATCH v4 0/5] MdeModulePkg: add support for non-discoverable devices Ard Biesheuvel
2016-11-25 15:42 ` [PATCH v4 1/5] MdeModulePkg: introduce non-discoverable device protocol Ard Biesheuvel
2016-11-28 1:57 ` Ni, Ruiyu
2016-11-25 15:42 ` [PATCH v4 2/5] MdeModulePkg: introduce helper library to register non-discoverable devices Ard Biesheuvel
2016-11-28 1:58 ` Ni, Ruiyu
2016-11-25 15:42 ` [PATCH v4 3/5] MdeModulePkg: implement generic PCI I/O driver for " Ard Biesheuvel
2016-11-28 1:56 ` Ni, Ruiyu
2016-11-30 14:06 ` Leif Lindholm
2016-12-02 10:09 ` Leif Lindholm
2016-12-02 12:54 ` Ni, Ruiyu [this message]
2016-12-02 14:40 ` Leif Lindholm
2016-12-02 15:07 ` Ard Biesheuvel
2016-12-02 15:56 ` Leif Lindholm
2016-12-02 18:42 ` Ard Biesheuvel
2016-12-05 9:35 ` Leif Lindholm
2016-11-25 15:42 ` [PATCH v4 4/5] MdeModulePkg/NonDiscoverablePciDeviceDxe: add support for non-coherent DMA Ard Biesheuvel
2016-11-28 2:25 ` Ni, Ruiyu
2016-11-25 15:42 ` [PATCH v4 5/5] Omap35xxPkg/PciEmulation: port to new non-discoverable device infrastructure Ard Biesheuvel
2016-11-27 10:18 ` [PATCH v4 0/5] MdeModulePkg: add support for non-discoverable devices Marcin Wojtas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=734D49CCEBEEF84792F5B80ED585239D58E926A5@SHSMSX104.ccr.corp.intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox