From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D991C21DFA7A9 for ; Sun, 26 Mar 2017 22:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490593241; x=1522129241; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=f5OVaNPDdxgaoCJog57wKxkpeCiGB1dAQT79FXYNPlk=; b=iG5u3oZqqd0LNu8CD31OLQvvfDfQ64eoM0IqJjZtoo9FA9t4pyrjNZfK PLHXxM+Gje+GZbunulgIHCiw1s3Rxg==; Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Mar 2017 22:40:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,229,1486454400"; d="scan'208";a="65368436" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 26 Mar 2017 22:40:40 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 26 Mar 2017 22:40:40 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 26 Mar 2017 22:40:40 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.42]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.224]) with mapi id 14.03.0248.002; Mon, 27 Mar 2017 13:39:56 +0800 From: "Ni, Ruiyu" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: Leo Duran , Brijesh Singh Thread-Topic: [RFC] [PATCH 3/3] MdeModulePkg/PciBus: Add IOMMU support. Thread-Index: AQHSpUo6pq+8Q3/dxkWzKCTsaKszNaGoLDgQ Date: Mon, 27 Mar 2017 05:39:56 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5B8EC287@SHSMSX104.ccr.corp.intel.com> References: <1490434122-16200-1-git-send-email-jiewen.yao@intel.com> <1490434122-16200-4-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1490434122-16200-4-git-send-email-jiewen.yao@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [RFC] [PATCH 3/3] MdeModulePkg/PciBus: Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Mar 2017 05:40:42 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable #1. If PciHostBridge driver doesn't consume IOMMU protocol, will the change= in PciBus driver cause any negative impact? For example, causing system hang? Do we need to int= roduce a bit to let PciHostBridge report the capability bit about IOMMU through PciHostBridge.GetAlloc= ationAttribute()? #2, Can you add a Maps field into the PciIoDevice structure? So that the Pc= iIoMapInfo can be inserted to the list and we can check whether the Mapping is invalid by checking= the existence in the list. This is better than checking the memory signature (PciIoMapInfo->Sig= nature). #3. I saw PciIo.Map/Allocate sets the IOMMU attribute and Unmap/Free clear= s the IOMMU attribute. Do we have the case that the original IOMMU attribute is not 0? If = that may happen, we may need to have an additional interface in IOMMU protocol to get the original = attribute. Thanks/Ray > -----Original Message----- > From: Yao, Jiewen > Sent: Saturday, March 25, 2017 5:29 PM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu ; Leo Duran ; > Brijesh Singh > Subject: [RFC] [PATCH 3/3] MdeModulePkg/PciBus: Add IOMMU support. >=20 > The responsibility of PciBus driver is to set IOMMU attribute, because on= ly > PciBus knows which device submits DMA access request. >=20 > PciBus driver assumes that PciHostBridge driver can allocate IOMMU page > aligned memory, if IOMMU protocol exists. >=20 > Cc: Ruiyu Ni > Cc: Leo Duran > Cc: Brijesh Singh > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 12 +++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 10 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 100 > ++++++++++++++++++++ > 4 files changed, 123 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > index f3be47a..c9ee4de 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > @@ -42,6 +42,8 @@ UINT64 gAllZero = =3D 0; >=20 > EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; > EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; > +EDKII_IOMMU_PROTOCOL *gIoMmuProtocol; > +UINTN mIoMmuPageSize =3D 1; >=20 >=20 > GLOBAL_REMOVE_IF_UNREFERENCED > EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugRequest =3D { @@ - > 256,6 +258,16 @@ PciBusDriverBindingStart ( > } >=20 > gBS->LocateProtocol ( > + &gEdkiiIoMmuProtocolGuid, > + NULL, > + (VOID **) &gIoMmuProtocol > + ); > + if (gIoMmuProtocol !=3D NULL) { > + gIoMmuProtocol->GetPageSize (gIoMmuProtocol, &mIoMmuPageSize); > + ASSERT ((mIoMmuPageSize & (mIoMmuPageSize - 1)) =3D=3D 0); } > + > + gBS->LocateProtocol ( > &gEfiIncompatiblePciDeviceSupportProtocolGuid, > NULL, > (VOID **) &gIncompatiblePciDeviceSupport diff --git > a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index 39ba8b9..6f96696 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. > #include > #include > #include > +#include >=20 > #include > #include @@ -304,6 +305,13 @@ struct > _PCI_IO_DEVICE { > CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE) >=20 >=20 > +#define PCI_IO_MAP_INFO_SIGNATURE SIGNATURE_32 ('p', 'm', 'a', 'p') > +typedef struct { > + UINT32 Signature; > + UINTN NumberOfBytes; > + EFI_PHYSICAL_ADDRESS DeviceAddress; > + VOID *PciRootBridgeIoMapping; > +} PCI_IO_MAP_INFO; >=20 > // > // Global Variables > @@ -319,6 +327,8 @@ extern UINT64 g= AllOne; > extern UINT64 gAllZero; > extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtoco= l; > extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtoco= l; > +extern EDKII_IOMMU_PROTOCOL *gIoMmuProtocol; > +extern UINTN mIoMmuPageSize; > extern BOOLEAN mReserveIsaAliases; > extern BOOLEAN mReserveVgaAliases; >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > index a3ab11f..5da094f 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -95,6 +95,7 @@ > gEfiPciRootBridgeIoProtocolGuid ## TO_START > gEfiIncompatiblePciDeviceSupportProtocolGuid ## > SOMETIMES_CONSUMES > gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES > + gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES >=20 > [FeaturePcd] > gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport ## > CONSUMES > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > index f72598d..01786c1 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c > @@ -967,6 +967,8 @@ PciIoMap ( > { > EFI_STATUS Status; > PCI_IO_DEVICE *PciIoDevice; > + PCI_IO_MAP_INFO *PciIoMapInfo; > + UINT64 IoMmuAttribute; >=20 > PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (This); >=20 > @@ -999,6 +1001,46 @@ PciIoMap ( > ); > } >=20 > + if (gIoMmuProtocol !=3D NULL) { > + if (!EFI_ERROR(Status)) { > + PciIoMapInfo =3D AllocatePool (sizeof(*PciIoMapInfo)); > + if (PciIoMapInfo =3D=3D NULL) { > + PciIoDevice->PciRootBridgeIo->Unmap (PciIoDevice->PciRootBridgeI= o, > *Mapping); > + return EFI_OUT_OF_RESOURCES; > + } > + > + PciIoMapInfo->Signature =3D PCI_IO_MAP_INFO_SIGNATURE= ; > + PciIoMapInfo->NumberOfBytes =3D *NumberOfBytes; > + PciIoMapInfo->DeviceAddress =3D *DeviceAddress; > + PciIoMapInfo->PciRootBridgeIoMapping =3D *Mapping; > + *Mapping =3D PciIoMapInfo; > + > + switch (Operation) { > + case EfiPciIoOperationBusMasterRead: > + IoMmuAttribute =3D EDKII_IOMMU_ATTRIBUTE_READ; > + break; > + case EfiPciIoOperationBusMasterWrite: > + IoMmuAttribute =3D EDKII_IOMMU_ATTRIBUTE_WRITE; > + break; > + case EfiPciIoOperationBusMasterCommonBuffer: > + IoMmuAttribute =3D EDKII_IOMMU_ATTRIBUTE_READ | > EDKII_IOMMU_ATTRIBUTE_WRITE; > + break; > + default: > + ASSERT(FALSE); > + return Status; > + } > + // > + // PciHostBridge should map IOMMU page aligned HostAddress. > + // > + gIoMmuProtocol->SetAttribute ( > + gIoMmuProtocol, > + PciIoDevice->Handle, > + PciIoMapInfo->DeviceAddress, > + ALIGN_VALUE(PciIoMapInfo->NumberOfBytes, > mIoMmuPageSize), > + IoMmuAttribute > + ); > + } > + } > return Status; > } >=20 > @@ -1021,9 +1063,19 @@ PciIoUnmap ( > { > EFI_STATUS Status; > PCI_IO_DEVICE *PciIoDevice; > + PCI_IO_MAP_INFO *PciIoMapInfo; >=20 > PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (This); >=20 > + PciIoMapInfo =3D NULL; > + if (gIoMmuProtocol !=3D NULL) { > + PciIoMapInfo =3D Mapping; > + if (PciIoMapInfo->Signature !=3D PCI_IO_MAP_INFO_SIGNATURE) { > + return EFI_INVALID_PARAMETER; > + } > + Mapping =3D PciIoMapInfo->PciRootBridgeIoMapping; > + } > + > Status =3D PciIoDevice->PciRootBridgeIo->Unmap ( > PciIoDevice->PciRootBridgeIo, > Mapping @@ -1037,6 +1089,22 @@= PciIoUnmap ( > ); > } >=20 > + if (gIoMmuProtocol !=3D NULL) { > + if (!EFI_ERROR(Status)) { > + // > + // PciHostBridge should map IOMMU page aligned HostAddress. > + // > + gIoMmuProtocol->SetAttribute ( > + gIoMmuProtocol, > + PciIoDevice->Handle, > + PciIoMapInfo->DeviceAddress, > + ALIGN_VALUE(PciIoMapInfo->NumberOfBytes, > mIoMmuPageSize), > + 0 > + ); > + FreePool (PciIoMapInfo); > + } > + } > + > return Status; > } >=20 > @@ -1073,6 +1141,7 @@ PciIoAllocateBuffer ( { > EFI_STATUS Status; > PCI_IO_DEVICE *PciIoDevice; > + UINTN Size; >=20 > if ((Attributes & > (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | > EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) !=3D 0){ @@ -1102,6 +1171,21 @@ > PciIoAllocateBuffer ( > ); > } >=20 > + if (gIoMmuProtocol !=3D NULL) { > + if (!EFI_ERROR(Status)) { > + // > + // PciHostBridge should allocate IOMMU page aligned HostAddress. > + // > + Size =3D EFI_PAGES_TO_SIZE(Pages); > + gIoMmuProtocol->SetAttribute ( > + gIoMmuProtocol, > + PciIoDevice->Handle, > + (UINTN)*HostAddress, > + ALIGN_VALUE(Size, mIoMmuPageSize), > + EDKII_IOMMU_ATTRIBUTE_READ | > EDKII_IOMMU_ATTRIBUTE_WRITE > + ); > + } > + } > return Status; > } >=20 > @@ -1127,6 +1211,7 @@ PciIoFreeBuffer ( > { > EFI_STATUS Status; > PCI_IO_DEVICE *PciIoDevice; > + UINTN Size; >=20 > PciIoDevice =3D PCI_IO_DEVICE_FROM_PCI_IO_THIS (This); >=20 > @@ -1144,6 +1229,21 @@ PciIoFreeBuffer ( > ); > } >=20 > + if (gIoMmuProtocol !=3D NULL) { > + if (!EFI_ERROR(Status)) { > + // > + // PciHostBridge should allocate IOMMU page aligned HostAddress. > + // > + Size =3D EFI_PAGES_TO_SIZE(Pages); > + gIoMmuProtocol->SetAttribute ( > + gIoMmuProtocol, > + PciIoDevice->Handle, > + (UINTN)HostAddress, > + ALIGN_VALUE(Size, mIoMmuPageSize), > + 0 > + ); > + } > + } > return Status; > } >=20 > -- > 2.7.4.windows.1