From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E057D21A18AA9 for ; Mon, 27 Mar 2017 19:24:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490667898; x=1522203898; h=from:to:cc:subject:date:message-id:references: in-reply-to:mime-version; bh=4NN6j4LgOUXdRqTPztaOvz2MtIp4Bz/cvCHpnupM5r0=; b=TQ6OsXobx4mRYYJKMn7CDicFjDMhAIeslS/+dxVy5CihYVAhbA2wDniW 6Bj3PzqigeWoL/nJ6Hm+8jaFEWvhNQ==; Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Mar 2017 19:24:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,234,1486454400"; d="scan'208,217";a="81286532" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga005.fm.intel.com with ESMTP; 27 Mar 2017 19:24:58 -0700 Received: from fmsmsx158.amr.corp.intel.com (10.18.116.75) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 19:24:58 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx158.amr.corp.intel.com (10.18.116.75) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 19:24:58 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.42]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.82]) with mapi id 14.03.0248.002; Tue, 28 Mar 2017 10:24:54 +0800 From: "Ni, Ruiyu" To: "Yao, Jiewen" , "Duran, Leo" , "edk2-devel@lists.01.org" CC: "Singh, Brijesh" Thread-Topic: [RFC] [PATCH 0/3] Add IOMMU support. Thread-Index: AQHSpUo4qDdW9oX2tE+04uXsQ068b6GolhYAgABhzACAAAP5gIAAjjfQ Date: Tue, 28 Mar 2017 02:24:53 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5B8ED126@SHSMSX104.ccr.corp.intel.com> References: <1490434122-16200-1-git-send-email-jiewen.yao@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503A914BF3@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503A914CA1@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503A914CA1@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [RFC] [PATCH 0/3] Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Mar 2017 02:24:59 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jiewen, For performance consideration, do you think we may define a bit as a hint t= o tell PciHostBridge (or PciBus, I don't know) whether a post-CopyMem is ne= eded? Thanks/Ray From: Yao, Jiewen Sent: Tuesday, March 28, 2017 9:55 AM To: Yao, Jiewen ; Duran, Leo ; edk= 2-devel@lists.01.org Cc: Ni, Ruiyu ; Singh, Brijesh Subject: RE: [RFC] [PATCH 0/3] Add IOMMU support. I forget mentioning that I have to do it in PciIo instead of PciRootBridgeI= o. The reason is that Intel VTd solution need know which PCI device submit the= DMA access request, so that it can only modify the IOMMU paging for this s= pecific device. I believe AMD IOMMU has similar requirement. However, this info is not needed, if you just want to enable AMD SEV soluti= on. In that case, you can ignore the DeviceHandle, and just update SEV clea= r/set bit for that memory. BTW: I just realize I miss one thing. I call gIoMmuProtocol->SetAttribute, = after it is returned from PciRootBridgeIo. For AMD SEC, I think we need do CopyMem again, if this is DMA read request.= I will update my patch for that. Thank you Yao Jiewen From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Yao,= Jiewen Sent: Tuesday, March 28, 2017 9:41 AM To: Duran, Leo >; edk2-devel@li= sts.01.org Cc: Ni, Ruiyu >; Singh, Brije= sh > Subject: Re: [edk2] [RFC] [PATCH 0/3] Add IOMMU support. Hi Leo I do intercept 4 I/O operation in *PciIo*, instead of *PciRootBridgeIo*. See: https://lists.01.org/pipermail/edk2-devel/2017-March/009021.html There are 4 gIoMmuProtocol->SetAttribute() I believe you can clear/set SEV = action there. Would you please double check that? Thank you Yao Jiewen From: Duran, Leo [mailto:leo.duran@amd.com] Sent: Tuesday, March 28, 2017 3:51 AM To: Yao, Jiewen >; edk2-d= evel@lists.01.org Cc: Ni, Ruiyu >; Singh, Brije= sh > Subject: RE: [RFC] [PATCH 0/3] Add IOMMU support. Hi Yao, This patch-set, in its current form, does not address all of the required S= EV functionality for PcIHostBridgeIo. Basically, we need to intercept all 4 I/O Operations: - IoMap() - IoUnmap() - IoAllocateBuffer() - IoFreeBuffer() SEV I/O intercepts would do this: 1) IoMap() - Allocate an accessible bounce buffer (AllocateType depends on consumer's = capabilities). - Clear SEV mask on retuned mapped DMA buffer - On DMA Read: CopyMem() from consumer buffer to mapped buffer (bounce oper= ation) 2) IoUnmap() - On DMA Write: CopyMem() from mapped buffer to consumer buffer (bounce ope= ration) - Restore SEV mask on mapped DMA buffer 3) IoAllocateBuffer() - Allocate an accessible buffer (AllocateType depends on consumer's capabil= ities). - Clear SEV mask on allocated buffer - return allocated buffer 4) IoFreeBuffer() - Restore SEV mask on allocated buffer - Free allocated buffer For an sample on how we've intercepted BmDmaLib operations, please refer to= the patch-sets posted by Brijesh: https://lists.01.org/pipermail/edk2-devel/2017-March/008838.html https://lists.01.org/pipermail/edk2-devel/2017-March/008840.html Thanks, Leo > -----Original Message----- > From: Jiewen Yao [mailto:jiewen.yao@intel.com] > Sent: Saturday, March 25, 2017 4:29 AM > To: edk2-devel@lists.01.org> > Cc: Ruiyu Ni >>; Duran, Leo >>; > Singh, Brijesh >> > Subject: [RFC] [PATCH 0/3] Add IOMMU support. > > This patch series adds IOMMU protocol and updates the consumer to > support IOMMU based DMA access in UEFI. > > This patch series can support the BmDmaLib request for AMD SEV. > submitted by Duran, Leo >> and Brijesh Singh > >>. > https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and > https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html. > We can have an AMD SEV specific IOMMU driver to produce IOMMU > protocol, and clear SEV in IOMMU->SetAttribute(). > > This patch series can also support Intel VTd based DMA protection, > requested by Jiewen Yao >>, discussed in > https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html. > We can have an Intel VTd specific IOMMU driver to produce IOMMU > protocol, and update VTd engine to grant or deny access in IOMMU- > >SetAttribute(). > > This patch series does not provide a full Intel VTd driver, which will be > provide in other patch in the future. > > The purpose of this patch series to review if this IOMMU protocol design = can > meet all DMA access and management requirement. > > Cc: Ruiyu Ni >> > Cc: Leo Duran >> > Cc: Brijesh Singh >> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao >> > > > Jiewen Yao (3): > MdeModulePkg/Include: Add IOMMU protocol definition. > MdeModulePkg/PciHostBridge: Add IOMMU support. > MdeModulePkg/PciBus: Add IOMMU support. > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 12 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 10 ++ > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 100 +++++++= +++++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 3 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 7 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 172 > +++++++++++++++++++- > MdeModulePkg/Include/Protocol/IoMmu.h | 132 > +++++++++++++++ > MdeModulePkg/MdeModulePkg.dec | 3 + > 10 files changed, 436 insertions(+), 5 deletions(-) create mode 100644 > MdeModulePkg/Include/Protocol/IoMmu.h > > -- > 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel