From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6171921A134AE for ; Thu, 4 May 2017 18:32:43 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 May 2017 18:32:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,290,1491289200"; d="scan'208";a="1164827118" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga002.fm.intel.com with ESMTP; 04 May 2017 18:32:42 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 4 May 2017 18:32:42 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.178]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.224]) with mapi id 14.03.0319.002; Fri, 5 May 2017 09:32:31 +0800 From: "Ni, Ruiyu" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: Leo Duran , Ard Biesheuvel Thread-Topic: [edk2] [PATCH V5 0/3] Add IOMMU support. Thread-Index: AQHSxPRUIdLLIsE5gEm7HGuncvPd6KHk9MhA Date: Fri, 5 May 2017 01:32:29 +0000 Deferred-Delivery: Fri, 5 May 2017 01:32:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5B93E058@SHSMSX104.ccr.corp.intel.com> References: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1493915561-8500-1-git-send-email-jiewen.yao@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH V5 0/3] Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 May 2017 01:32:43 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Jiewen Yao > Sent: Friday, May 5, 2017 12:33 AM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu ; Leo Duran ; Ard > Biesheuvel > Subject: [edk2] [PATCH V5 0/3] Add IOMMU support. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V5 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > Minor update from V4. >=20 > 1) Remove unused SetAttribute() API in IOMMU protocol. > (Feedback from Ruiyu and Ard) > 2) Rename SetMappingAttribute() to SetAttribute(). > (Feedback from Ruiyu) > 3) Fix the bug in PciBus driver for Operation (Thanks to Ard to catch it) >=20 > V4: > Tested-by: Brijesh Singh With the issue in 3/3 > addressed: > Tested-by: Ard Biesheuvel >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V4 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > Refine the EDKII_IOMMU_PROTOCOL. >=20 > 1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API. > They are similar to DmaLib in EmbeddedPkg and similar to the previous > BmDmaLib (by leo.duran@amd.com). >=20 > These APIs are invoked by PciHostBridge driver to allocate DMA memory. >=20 > The PciHostBridge driver (IOMMU consumer) is simplified: > It uses IOMMU, if IOMMU protocol is present. > Else it uses original logic. >=20 > 2) Add SetMappingAttribute() API. > It is similar to SetAttribute() API in V1. >=20 > This API is invoked by PciBus driver to set DMA access attribute (read/wr= ite) for > device. >=20 > The PciBus driver (IOMMU consumer) is simplified: > It sets access attribute in Map/Unmap, > if IOMMU protocol is present. >=20 > 3) Remove SetRemapAddress/GetRemapAddress() API. > Because PciHostBridge/PciBus can call the APIs defined above, there is no= need > to provide remap capability. >=20 > -- Sample producer drivers: > 1) The sample VTd driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdDxe >=20 > It is added to show the concept. It is not fully implemented yet. > It will not be checked in in this patch. >=20 > 2) The sample AMD SEV driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmdSevDx > e > (code is borrowed from leo.duran@amd.com and brijesh.singh@amd.com) >=20 > This is not a right place to put this driver. >=20 > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. >=20 > 3) The sample STYX driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleStyxDxe > (code is borrowed from ard.biesheuvel@linaro.org) >=20 > This is not a right place to put this driver. >=20 > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. >=20 >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V3 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Add Remap capability (from Ard Biesheuvel) Add > EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL. >=20 > NOTE: The code is not fully validated yet. > The purpose is to collect feedback to decide the next step. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V2 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Enhance Unmap() in PciIo (From Ruiyu Ni) Maintain a local list of MapI= nfo and > match it in Unmap. >=20 > 2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran) Fix = a bug > in V1 that copy mem for read happen before SetAttribute, which will break= AMD > SEV solution. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V1 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D >=20 > This patch series adds IOMMU protocol and updates the consumer to support > IOMMU based DMA access in UEFI. >=20 > This patch series can support the BmDmaLib request for AMD SEV. > submitted by Duran, Leo and Brijesh Singh > . > https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and > https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html. > We can have an AMD SEV specific IOMMU driver to produce IOMMU protocol, > and clear SEV in IOMMU->SetAttribute(). >=20 > This patch series can also support Intel VTd based DMA protection, reques= ted by > Jiewen Yao , discussed in > https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html. > We can have an Intel VTd specific IOMMU driver to produce IOMMU protocol, > and update VTd engine to grant or deny access in IOMMU->SetAttribute(). >=20 > This patch series does not provide a full Intel VTd driver, which will be= provide in > other patch in the future. >=20 > The purpose of this patch series to review if this IOMMU protocol design = can > meet all DMA access and management requirement. >=20 > Cc: Ruiyu Ni > Cc: Leo Duran > Cc: Brijesh Singh > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao >=20 > Jiewen Yao (3): > MdeModulePkg/Include: Add IOMMU protocol definition. > MdeModulePkg/PciHostBridge: Add IOMMU support. > MdeModulePkg/PciBus: Add IOMMU support. >=20 > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 9 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 47 +++- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 37 +++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 61 +++++ > MdeModulePkg/Include/Protocol/IoMmu.h | 259 > ++++++++++++++++++++ > MdeModulePkg/MdeModulePkg.dec | 3 + > 10 files changed, 418 insertions(+), 4 deletions(-) create mode 100644 > MdeModulePkg/Include/Protocol/IoMmu.h >=20 > -- > 2.7.4.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel