From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9402521CE7417 for ; Sun, 6 Aug 2017 23:26:56 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Aug 2017 23:29:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,336,1498546800"; d="scan'208";a="887243869" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by FMSMGA003.fm.intel.com with ESMTP; 06 Aug 2017 23:29:11 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 Aug 2017 23:29:11 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 Aug 2017 23:29:11 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.151]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.116]) with mapi id 14.03.0319.002; Mon, 7 Aug 2017 14:29:09 +0800 From: "Ni, Ruiyu" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Fan, Jeff" , "Wei, David" Thread-Topic: [Patch 2/7] Vlv2TbltDevicePkg: Enhance get mtrr mask logic. Thread-Index: AQHTDDtvVtdChWwYvkSqVlJ5/H1BFKJ4dFhw Date: Mon, 7 Aug 2017 06:29:09 +0000 Deferred-Delivery: Mon, 7 Aug 2017 06:29:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5B9CE281@SHSMSX104.ccr.corp.intel.com> References: <1501752726-14072-1-git-send-email-eric.dong@intel.com> <1501752726-14072-3-git-send-email-eric.dong@intel.com> In-Reply-To: <1501752726-14072-3-git-send-email-eric.dong@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 2/7] Vlv2TbltDevicePkg: Enhance get mtrr mask logic. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 06:26:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: Dong, Eric > Sent: Thursday, August 3, 2017 5:32 PM > To: edk2-devel@lists.01.org > Cc: Fan, Jeff ; Ni, Ruiyu ; Wei, > David > Subject: [Patch 2/7] Vlv2TbltDevicePkg: Enhance get mtrr mask logic. >=20 > In order to not use the deprecated macro, refine get mtrr mask value logi= c. >=20 > Cc: Jeff Fan > Cc: Ruiyu Ni > Cc: David Wei > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Eric Dong > --- > Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c | 45 > ++++++++++++++++++++++---- > 1 file changed, 38 insertions(+), 7 deletions(-) >=20 > diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c > b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c > index 99bdeb1..5a18a3f 100644 > --- a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c > +++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c > @@ -70,6 +70,34 @@ GetMemorySize ( > ); >=20 >=20 > +/** > + Initializes the valid address mask for MTRRs. > + > + This function initializes the valid bits mask and valid address mask f= or > MTRRs. > + > +**/ > +UINT64 > +InitializeAddressMtrrMask ( > + VOID > + ) > +{ > + UINT32 RegEax; > + UINT8 PhysicalAddressBits; > + UINT64 ValidMtrrBitsMask; > + > + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); > + > + if (RegEax >=3D 0x80000008) { > + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); > + > + PhysicalAddressBits =3D (UINT8) RegEax; } else { > + PhysicalAddressBits =3D 36; > + } > + > + ValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1; > + return (ValidMtrrBitsMask & 0xfffffffffffff000ULL); } >=20 > EFI_STATUS > EFIAPI > @@ -89,6 +117,7 @@ SetPeiCacheMode ( > UINT64 HighMemoryLength; > UINT8 Index; > MTRR_SETTINGS MtrrSetting; > + UINT64 ValidMtrrAddressMask; >=20 > // > // Load Cache PPI > @@ -124,6 +153,8 @@ SetPeiCacheMode ( > &BootMode > ); >=20 > + ValidMtrrAddressMask =3D InitializeAddressMtrrMask (); > + > // > // Determine memory usage > // > @@ -166,15 +197,15 @@ SetPeiCacheMode ( > // > Index =3D 0; > MtrrSetting.Variables.Mtrr[0].Base =3D (FixedPcdGet32 > (PcdFlashAreaBaseAddress) | CacheWriteProtected); > - MtrrSetting.Variables.Mtrr[0].Mask =3D ((~((UINT64)(FixedPcdGet32 > (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | > MTRR_LIB_CACHE_MTRR_ENABLED; > + MtrrSetting.Variables.Mtrr[0].Mask =3D ((~((UINT64)(FixedPcdGet32 > + (PcdFlashAreaSize) - 1))) & ValidMtrrAddressMask) | > + MTRR_LIB_CACHE_MTRR_ENABLED; > Index ++; >=20 > MemOverflow =3D0; > while (MaxMemoryLength > MemOverflow){ > - MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & > MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; > + MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & > + ValidMtrrAddressMask) | CacheWriteBack; > MemoryLength =3D MaxMemoryLength - MemOverflow; > MemoryLength =3D GetPowerOfTwo64 (MemoryLength); > - MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & > MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; > + MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & > + ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; >=20 > MemOverflow +=3D MemoryLength; > Index++; > @@ -185,15 +216,15 @@ SetPeiCacheMode ( > while (MaxMemoryLength !=3D MemoryLength) { > MemoryLengthUc =3D GetPowerOfTwo64 (MaxMemoryLength - > MemoryLength); >=20 > - MtrrSetting.Variables.Mtrr[Index].Base =3D ((MaxMemoryLength - > MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | > CacheUncacheable; > - MtrrSetting.Variables.Mtrr[Index].Mask=3D ((~(MemoryLengthUc - 1))= & > MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; > + MtrrSetting.Variables.Mtrr[Index].Base =3D ((MaxMemoryLength - > MemoryLengthUc) & ValidMtrrAddressMask) | CacheUncacheable; > + MtrrSetting.Variables.Mtrr[Index].Mask=3D ((~(MemoryLengthUc - 1))= & > ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; > MaxMemoryLength -=3D MemoryLengthUc; > Index++; > } >=20 > MemOverflow =3D0x100000000; > while (HighMemoryLength > 0) { > - MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & > MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack; > + MtrrSetting.Variables.Mtrr[Index].Base =3D (MemOverflow & > + ValidMtrrAddressMask) | CacheWriteBack; > MemoryLength =3D HighMemoryLength; > MemoryLength =3D GetPowerOfTwo64 (MemoryLength); >=20 > @@ -201,7 +232,7 @@ SetPeiCacheMode ( > MemoryLength =3D MemOverflow; > } >=20 > - MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & > MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED; > + MtrrSetting.Variables.Mtrr[Index].Mask =3D ((~(MemoryLength - 1)) & > + ValidMtrrAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED; >=20 > MemOverflow +=3D MemoryLength; > HighMemoryLength -=3D MemoryLength; > -- > 2.7.0.windows.1