From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4E2AB21CE7417 for ; Sun, 6 Aug 2017 23:26:56 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 06 Aug 2017 23:29:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,336,1498546800"; d="scan'208";a="1202781601" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 06 Aug 2017 23:29:11 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 Aug 2017 23:29:11 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 6 Aug 2017 23:29:11 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.151]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.122]) with mapi id 14.03.0319.002; Mon, 7 Aug 2017 14:29:09 +0800 From: "Ni, Ruiyu" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Fan, Jeff" Thread-Topic: [Patch 3/7] UefiCpuPkg CpuDxe: Enhance get mtrr mask logic. Thread-Index: AQHTDDtvACCiVmmYBEm3llW2bTP5j6J4dF3Q Date: Mon, 7 Aug 2017 06:29:09 +0000 Deferred-Delivery: Mon, 7 Aug 2017 06:29:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5B9CE286@SHSMSX104.ccr.corp.intel.com> References: <1501752726-14072-1-git-send-email-eric.dong@intel.com> <1501752726-14072-4-git-send-email-eric.dong@intel.com> In-Reply-To: <1501752726-14072-4-git-send-email-eric.dong@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 3/7] UefiCpuPkg CpuDxe: Enhance get mtrr mask logic. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2017 06:26:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: Dong, Eric > Sent: Thursday, August 3, 2017 5:32 PM > To: edk2-devel@lists.01.org > Cc: Fan, Jeff ; Ni, Ruiyu > Subject: [Patch 3/7] UefiCpuPkg CpuDxe: Enhance get mtrr mask logic. >=20 > In order to not use the deprecated macro, refine get mtrr mask value logi= c. >=20 > Cc: Jeff Fan > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Eric Dong > --- > UefiCpuPkg/CpuDxe/CpuDxe.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c > index 8680656..6218670 100644 > --- a/UefiCpuPkg/CpuDxe/CpuDxe.c > +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c > @@ -25,8 +25,8 @@ > BOOLEAN InterruptState =3D FALSE; > EFI_HANDLE mCpuHandle =3D NULL; > BOOLEAN mIsFlushingGCD; > -UINT64 mValidMtrrAddressMask =3D > MTRR_LIB_CACHE_VALID_ADDRESS; > -UINT64 mValidMtrrBitsMask =3D MTRR_LIB_MSR_VALID_M= ASK; > +UINT64 mValidMtrrAddressMask; > +UINT64 mValidMtrrBitsMask; > UINT64 mTimerPeriod =3D 0; >=20 > FIXED_MTRR mFixedMtrrTable[] =3D { > @@ -510,13 +510,12 @@ InitializeMtrrMask ( > AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); >=20 > PhysicalAddressBits =3D (UINT8) RegEax; > - > - mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1; > - mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL= ; > } else { > - mValidMtrrBitsMask =3D MTRR_LIB_MSR_VALID_MASK; > - mValidMtrrAddressMask =3D MTRR_LIB_CACHE_VALID_ADDRESS; > + PhysicalAddressBits =3D 36; > } > + > + mValidMtrrBitsMask =3D LShiftU64 (1, PhysicalAddressBits) - 1; > + mValidMtrrAddressMask =3D mValidMtrrBitsMask & 0xfffffffffffff000ULL; > } >=20 > /** > -- > 2.7.0.windows.1