From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 172FF21F303FB for ; Thu, 28 Sep 2017 17:52:44 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2017 17:56:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,451,1500966000"; d="scan'208";a="904950333" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 28 Sep 2017 17:55:59 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 17:55:59 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 17:55:59 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.152]) with mapi id 14.03.0319.002; Fri, 29 Sep 2017 08:55:45 +0800 From: "Ni, Ruiyu" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" Thread-Topic: [Patch v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. Thread-Index: AQHTOLmqie9DOd4yWUemxv4H7sO+kKLLCaVA Date: Fri, 29 Sep 2017 00:55:44 +0000 Deferred-Delivery: Fri, 29 Sep 2017 00:55:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BA6F59E@SHSMSX103.ccr.corp.intel.com> References: <1506644796-11288-1-git-send-email-eric.dong@intel.com> <1506644796-11288-2-git-send-email-eric.dong@intel.com> In-Reply-To: <1506644796-11288-2-git-send-email-eric.dong@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 00:52:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni -----Original Message----- From: Dong, Eric=20 Sent: Friday, September 29, 2017 8:27 AM To: edk2-devel@lists.01.org Cc: Yao, Jiewen ; Ni, Ruiyu Subject: [Patch v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. In S3 resume path, current implementation do 2 separate INIT-SIPI-SIPI, thi= s is not necessary. This change combine these 2 INIT-SIPI-SIPI to 1 and add= CpuPause between them. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 51 ++++++++++++++++++++---------------= ---- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 9404501..ae4b516 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -39,6 +39,11 @@ typedef struct { // SPIN_LOCK *mMemoryMappedLock =3D NULL; =20 +// +// Signal that SMM BASE relocation is complete. +// +volatile BOOLEAN mInitApsAfterSmmBaseReloc; + /** Get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned. @@ -342,17 +347,21 @@ SetProcessorRegister ( } } =20 + + /** - AP initialization before SMBASE relocation in the S3 boot path. + AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ VOID -EarlyMPRendezvousProcedure ( +MPRendezvousProcedure ( VOID ) { CPU_REGISTER_TABLE *RegisterTableList; UINT32 InitApicId; UINTN Index; + UINTN TopOfStack; + UINT8 Stack[128]; =20 LoadMtrrData (mAcpiCpuData.MtrrTable); =20 @@ -368,25 +377,18 @@ EarlyMPRendezvousProcedure ( } } =20 + // // Count down the number with lock mechanism. // InterlockedDecrement (&mNumberToFinish); -} =20 -/** - AP initialization after SMBASE relocation in the S3 boot path. -**/ -VOID -MPRendezvousProcedure ( - VOID - ) -{ - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - UINTN TopOfStack; - UINT8 Stack[128]; + // + // Wait for BSP to signal SMM Base relocation done. + // + while (!mInitApsAfterSmmBaseReloc) { + CpuPause (); + } =20 ProgramVirtualWireMode (); DisableLvtInterrupts (); @@ -500,7 +502,12 @@ EarlyInitializeCpu ( PrepareApStartupVector (mAcpiCpuData.StartupVector); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) EarlyMPRendezvousProcedu= re; + mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; + + // + // Execute code for before SmmBaseReloc. Note: This flag is maintained a= cross S3 boots. + // + mInitApsAfterSmmBaseReloc =3D FALSE; =20 // // Send INIT IPI - SIPI to all APs @@ -538,17 +545,11 @@ InitializeCpu ( } =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - // - // StackStart was updated when APs were waken up in EarlyInitializeCpu. - // Re-initialize StackAddress to original beginning address. - // - mExchangeInfo->StackStart =3D (VOID *) (UINTN) mAcpiCpuData.StackAddres= s; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; =20 // - // Send INIT IPI - SIPI to all APs + // Signal that SMM base relocation is complete and to continue initializ= ation. // - SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); + mInitApsAfterSmmBaseReloc =3D TRUE; =20 while (mNumberToFinish > 0) { CpuPause (); -- 2.7.0.windows.1