From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F2AC021F303FB for ; Thu, 28 Sep 2017 17:52:32 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 28 Sep 2017 17:55:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,451,1500966000"; d="scan'208";a="1225015389" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 28 Sep 2017 17:55:47 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 17:55:48 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 17:55:47 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Fri, 29 Sep 2017 08:55:45 +0800 From: "Ni, Ruiyu" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" Thread-Topic: [Patch v2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code. Thread-Index: AQHTOLmqyO3sukR50Ui7kJfsiasPSaLLCacg Date: Fri, 29 Sep 2017 00:55:44 +0000 Deferred-Delivery: Fri, 29 Sep 2017 00:55:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BA6F5A3@SHSMSX103.ccr.corp.intel.com> References: <1506644796-11288-1-git-send-email-eric.dong@intel.com> <1506644796-11288-3-git-send-email-eric.dong@intel.com> In-Reply-To: <1506644796-11288-3-git-send-email-eric.dong@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch v2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 00:52:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni -----Original Message----- From: Dong, Eric=20 Sent: Friday, September 29, 2017 8:27 AM To: edk2-devel@lists.01.org Cc: Yao, Jiewen ; Ni, Ruiyu Subject: [Patch v2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid dup= licated code. V2: Change function parameter to avoid touch global info in function. Enhance function name, make it more user friendly V1: Refine code to avoid duplicate code to set processor register. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 84 +++++++++++------------------------= ---- 1 file changed, 24 insertions(+), 60 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index ae4b516..ef72b9b 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -208,18 +208,30 @@ Returns: =20 This function programs registers for the calling processor. =20 - @param RegisterTable Pointer to register table of the running processor= . + @param RegisterTables Pointer to register table of the running p= rocessor. + @param RegisterTableCount Register table count. =20 **/ VOID SetProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable + IN CPU_REGISTER_TABLE *RegisterTables, + IN UINTN RegisterTableCount ) { CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; UINTN Index; UINTN Value; SPIN_LOCK *MsrSpinLock; + UINT32 InitApicId; + CPU_REGISTER_TABLE *RegisterTable; + + InitApicId =3D GetInitialApicId (); + for (Index =3D 0; Index < RegisterTableCount; Index++) { + if (RegisterTables[Index].InitialApicId =3D=3D InitApicId) { + RegisterTable =3D &RegisterTables[Index]; + break; + } + } =20 // // Traverse Register Table of this logical processor @@ -347,36 +359,20 = @@ SetProcessorRegister ( } } =20 - - /** AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ VOID -MPRendezvousProcedure ( +InitializeAp ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; UINTN TopOfStack; UINT8 Stack[128]; =20 LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } - + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus); =20 // // Count down the number with lock mechanism. @@ -393,14 +389,7 @@ MPRendezvousProcedure ( ProgramVirtualWireMode (); DisableLvtInterrupts (); =20 - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus); =20 // // Place AP into the safe code, count down the number with lock mechanis= m in the safe code. @@ -475,34 +464,20 @@ PrepareApStartupVector ( =20 **/ VOID -EarlyInitializeCpu ( +InitializeCpuBeforeRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus); =20 ProgramVirtualWireMode (); =20 PrepareApStartupVector (mAcpiCpuData.StartupVector); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; + mExchangeInfo->ApFunction =3D (VOID *) (UINTN) InitializeAp; =20 // // Execute code for before SmmBaseReloc. Note: This flag is maintained a= cross S3 boots. @@ -527,22 +502,11 @@ EarlyInitializeCpu ( =20 **/ VOID -InitializeCpu ( +InitializeCpuAfterRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.RegisterTable, mAcpiCpuData.NumberOfCpus); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; =20 @@ -660,7 +624,7 @@ SmmRestoreCpu ( // // First time microcode load and restore MTRRs // - EarlyInitializeCpu (); + InitializeCpuBeforeRebase (); } =20 // @@ -675,7 +639,7 @@ SmmRestoreCpu ( // // Restore MSRs for BSP and all APs // - InitializeCpu (); + InitializeCpuAfterRebase (); } =20 // -- 2.7.0.windows.1