From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E80FE2222758A for ; Sun, 7 Jan 2018 21:56:32 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jan 2018 22:01:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,329,1511856000"; d="scan'208";a="8283188" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga002.fm.intel.com with ESMTP; 07 Jan 2018 22:01:41 -0800 Received: from fmsmsx158.amr.corp.intel.com (10.18.116.75) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 7 Jan 2018 22:01:41 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx158.amr.corp.intel.com (10.18.116.75) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 7 Jan 2018 22:01:41 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Mon, 8 Jan 2018 14:01:39 +0800 From: "Ni, Ruiyu" To: Meenakshi Aggarwal , "ard.biesheuvel@linaro.org" , "Gao, Liming" , "Kinney, Michael D" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] PCI : define macro for AHCI base address. Thread-Index: AQHTiEIq9sb2Jp5Kf0G1JqmJydNwsqNpeZpQ Date: Mon, 8 Jan 2018 06:01:38 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BB1E5C9@SHSMSX104.ccr.corp.intel.com> References: <1515410446-14750-1-git-send-email-meenakshi.aggarwal@nxp.com> In-Reply-To: <1515410446-14750-1-git-send-email-meenakshi.aggarwal@nxp.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] PCI : define macro for AHCI base address. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Jan 2018 05:56:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please do not put this AHCI specific macro in Pci22.h. I think only AtaAtapiPassThru driver needs to access the AHCI BAR, There seems no need to expose this definition to public. Thanks/Ray > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Meenakshi Aggarwal > Sent: Monday, January 8, 2018 7:21 PM > To: ard.biesheuvel@linaro.org; Gao, Liming ; Kinney= , > Michael D ; edk2-devel@lists.01.org > Subject: [edk2] [PATCH] PCI : define macro for AHCI base address. >=20 > Define PCI BAR 5 macro of AHCI Base address. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal > --- > MdePkg/Include/IndustryStandard/Pci22.h | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/MdePkg/Include/IndustryStandard/Pci22.h > b/MdePkg/Include/IndustryStandard/Pci22.h > index 96a7680..a63bb7c 100644 > --- a/MdePkg/Include/IndustryStandard/Pci22.h > +++ b/MdePkg/Include/IndustryStandard/Pci22.h > @@ -533,6 +533,7 @@ typedef struct { > #define PCI_HEADER_TYPE_OFFSET 0x0E > #define PCI_BIST_OFFSET 0x0F > #define PCI_BASE_ADDRESSREG_OFFSET 0x10 > +#define PCI_AHCI_BASE_ADDRESS 0x24 > #define PCI_CARDBUS_CIS_OFFSET 0x28 > #define PCI_SVID_OFFSET 0x2C ///< SubSystem = Vendor id > #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C > -- > 1.9.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel