Re: [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode

["Ni, Ruiyu" <ruiyu.ni@intel.com>]

Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

Thanks/Ray

> -----Original Message-----
> From: edk2-devel <edk2-devel-bounces@lists.01.org> On Behalf Of Leo
> Duran
> Sent: Friday, May 25, 2018 3:08 AM
> To: edk2-devel@lists.01.org
> Cc: Dong, Eric <eric.dong@intel.com>; Zeng, Star <star.zeng@intel.com>
> Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550:
> Ensure FIFO Polled Mode
> 
> Put the UART in FIFO Polled Mode by clearing IER after setting FCR.
> Also, add comments to show DLAB state for registers 0 and 1.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> Cc: Star Zeng <star.zeng@intel.com>
> CC: Eric Dong <eric.dong@intel.com>
> ---
>  .../BaseSerialPortLib16550/BaseSerialPortLib16550.c      | 16 ++++++++++++--
> --
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git
> a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> index 0ccac96..6532c4d 100644
> ---
> a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> +++
> b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
> @@ -3,6 +3,8 @@
> 
>    (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
>    Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
> +
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD
> License
>    which accompanies this distribution.  The full text of the license may be
> found at
> @@ -30,10 +32,11 @@
>  //
>  // 16550 UART register offsets and bitfields
>  //
> -#define R_UART_RXBUF          0
> -#define R_UART_TXBUF          0
> -#define R_UART_BAUD_LOW       0
> -#define R_UART_BAUD_HIGH      1
> +#define R_UART_RXBUF          0   // LCR_DLAB = 0
> +#define R_UART_TXBUF          0   // LCR_DLAB = 0
> +#define R_UART_BAUD_LOW       0   // LCR_DLAB = 1
> +#define R_UART_BAUD_HIGH      1   // LCR_DLAB = 1
> +#define R_UART_IER            1   // LCR_DLAB = 0
>  #define R_UART_FCR            2
>  #define   B_UART_FCR_FIFOE    BIT0
>  #define   B_UART_FCR_FIFO64   BIT5
> @@ -554,6 +557,11 @@ SerialPortInitialize (
>    SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR,
> (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE |
> B_UART_FCR_FIFO64)));
> 
>    //
> +  // Set FIFO Polled Mode by clearing IER after setting FCR
> +  //
> +  SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00);
> +
> +  //
>    // Put Modem Control Register(MCR) into its reset state of 0x00.
>    //
>    SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);
> --
> 2.7.4
> 
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