From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A5FD8203B9907 for ; Fri, 25 May 2018 01:20:32 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 May 2018 01:20:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,439,1520924400"; d="scan'208";a="53753844" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 25 May 2018 01:20:31 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 25 May 2018 01:20:31 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 25 May 2018 01:20:30 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.240]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.96]) with mapi id 14.03.0319.002; Fri, 25 May 2018 16:20:29 +0800 From: "Ni, Ruiyu" To: Leo Duran , "edk2-devel@lists.01.org" CC: "Dong, Eric" , "Zeng, Star" Thread-Topic: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Thread-Index: AQHT85KFGUgZUIqyIkWKBiF2fb7lD6RAGvQQ Date: Fri, 25 May 2018 08:20:28 +0000 Deferred-Delivery: Fri, 25 May 2018 08:20:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BCAA265@SHSMSX104.ccr.corp.intel.com> References: <1527188850-4553-1-git-send-email-leo.duran@amd.com> <1527188850-4553-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1527188850-4553-2-git-send-email-leo.duran@amd.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 May 2018 08:20:32 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: edk2-devel On Behalf Of Leo > Duran > Sent: Friday, May 25, 2018 3:08 AM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; Zeng, Star > Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Put the UART in FIFO Polled Mode by clearing IER after setting FCR. > Also, add comments to show DLAB state for registers 0 and 1. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leo Duran > Cc: Star Zeng > CC: Eric Dong > --- > .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++= ++-- > -- > 1 file changed, 12 insertions(+), 4 deletions(-) >=20 > diff --git > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > index 0ccac96..6532c4d 100644 > --- > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > +++ > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > @@ -3,6 +3,8 @@ >=20 > (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
> Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2018, AMD Incorporated. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at > @@ -30,10 +32,11 @@ > // > // 16550 UART register offsets and bitfields > // > -#define R_UART_RXBUF 0 > -#define R_UART_TXBUF 0 > -#define R_UART_BAUD_LOW 0 > -#define R_UART_BAUD_HIGH 1 > +#define R_UART_RXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_TXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_BAUD_LOW 0 // LCR_DLAB =3D 1 > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB =3D 1 > +#define R_UART_IER 1 // LCR_DLAB =3D 0 > #define R_UART_FCR 2 > #define B_UART_FCR_FIFOE BIT0 > #define B_UART_FCR_FIFO64 BIT5 > @@ -554,6 +557,11 @@ SerialPortInitialize ( > SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, > (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | > B_UART_FCR_FIFO64))); >=20 > // > + // Set FIFO Polled Mode by clearing IER after setting FCR > + // > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); > + > + // > // Put Modem Control Register(MCR) into its reset state of 0x00. > // > SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel