From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A8E6E210FC0B7 for ; Wed, 13 Jun 2018 22:40:01 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 22:40:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,222,1526367600"; d="scan'208";a="63037730" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga004.fm.intel.com with ESMTP; 13 Jun 2018 22:40:00 -0700 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Jun 2018 22:40:00 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Jun 2018 22:40:00 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.87]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.70]) with mapi id 14.03.0319.002; Thu, 14 Jun 2018 13:39:58 +0800 From: "Ni, Ruiyu" To: Paolo Bonzini , Laszlo Ersek , "Leo Duran" , "edk2-devel@lists.01.org" CC: "Justen, Jordan L" , Brijesh Singh , Jeff Fan , "Gao, Liming" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors. Thread-Index: AQHUA1LJzgKSzzw5lEiGCr52gNIDeqReI1OAgAAAv4CAARlmAA== Date: Thu, 14 Jun 2018 05:39:57 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BD33EEB@SHSMSX104.ccr.corp.intel.com> References: <1528920674-24912-1-git-send-email-leo.duran@amd.com> <1528920674-24912-2-git-send-email-leo.duran@amd.com> <9e2b3f74-c37e-06d9-293e-04976713ce8c@redhat.com> <6e4e65de-ef6c-a94a-b94c-aa3572a31dcf@redhat.com> In-Reply-To: <6e4e65de-ef6c-a94a-b94c-aa3572a31dcf@redhat.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jun 2018 05:40:01 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks/Ray > -----Original Message----- > From: edk2-devel On Behalf Of Paolo > Bonzini > Sent: Thursday, June 14, 2018 4:52 AM > To: Laszlo Ersek ; Leo Duran ; > edk2-devel@lists.01.org > Cc: Justen, Jordan L ; Brijesh Singh > ; Jeff Fan ; Gao, Liming > > Subject: Re: [edk2] [PATCH] UefiCpuPkg/LocalApicLib: Exclude second > SendIpi sequence on AMD processors. >=20 > On 13/06/2018 22:49, Laszlo Ersek wrote: > > Hello Leo, > > > > On 06/13/18 22:11, Leo Duran wrote: > >> On AMD processors the second SendIpi in the SendInitSipiSipi and > >> SendInitSipiSipiAllExcludingSelf routines is not required, and may > >> cause undesired side-effects during MP initialization. > >> > >> This patch leverages the StandardSignatureIsAuthenticAMD check to > >> exclude the second SendIpi and its associated MicroSecondDelay (200). > > > > QEMU and KVM emulate some AMD processors too; of particular interest > > is the recent EPYC addition, I believe (for SME/SEV, minimally). > > > > Did you check whether the StandardSignatureIsAuthenticAMD() check > > applies to those QEMU VCPU models, and if so, whether omitting the > > second Startup IPI interferes with *V*CPU startup in OVMF guests? (In > > multiprocessing modules, such as CpuMpPei, CpuDxe, and > > PiSmmCpuDxeSmm.) > > > > Adding Brijesh, Paolo and Igor. >=20 > Actually I would be surprised if any recent processor needs the INIT-SIPI= -SIPI > (though I'm not sure what undesired side effects it might trigger). Why the recent processors don't need INIT-SIPI-SIPI? I thought it is the only way to wake up processors when it's halted (HLT). >=20 > Paolo > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel