From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D5B421B02822 for ; Tue, 14 Aug 2018 22:41:14 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2018 22:41:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,241,1531810800"; d="scan'208";a="83475073" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga002.jf.intel.com with ESMTP; 14 Aug 2018 22:41:14 -0700 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 14 Aug 2018 22:41:14 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 14 Aug 2018 22:41:13 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.240]) with mapi id 14.03.0319.002; Wed, 15 Aug 2018 13:41:01 +0800 From: "Ni, Ruiyu" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: Laszlo Ersek Thread-Topic: [edk2] [Patch v4 1/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use GDT/IDT saved in Smram. Thread-Index: AQHUND3F6M9M94wRfE6xWKH9eVHdraTATFeQ Date: Wed, 15 Aug 2018 05:40:53 +0000 Deferred-Delivery: Wed, 15 Aug 2018 05:41:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BDD5229@SHSMSX104.ccr.corp.intel.com> References: <20180815021435.13748-1-eric.dong@intel.com> <20180815021435.13748-2-eric.dong@intel.com> In-Reply-To: <20180815021435.13748-2-eric.dong@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch v4 1/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use GDT/IDT saved in Smram. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Aug 2018 05:41:15 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: edk2-devel On Behalf Of Eric Dong > Sent: Wednesday, August 15, 2018 10:15 AM > To: edk2-devel@lists.01.org > Cc: Ni, Ruiyu ; Laszlo Ersek > Subject: [edk2] [Patch v4 1/5] UefiCpuPkg/PiSmmCpuDxeSmm: Use GDT/IDT > saved in Smram. >=20 > Current implementation will copy GDT/IDT at SmmReadyToLock point from ACP= I > NVS memory to Smram. Later at S3 resume phase, it restore the memory save= d > in Smram to ACPI NVS. It can directly use GDT/IDT saved in Smram instead = of > restore the original ACPI NVS memory. > This patch do this change. >=20 > V4 changes: > 1. Remove global variables > mGdtForAp/mIdtForAp/mMachineCheckHandlerForAp. >=20 > Test Done: > Do the OS boot and S3 resume test. >=20 > Cc: Laszlo Ersek > Cc: Ruiyu Ni > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > --- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 31 ++++++++++++++----------------- > 1 file changed, 14 insertions(+), 17 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > index 0b8ef70359..abd8a5a07b 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > @@ -66,9 +66,6 @@ ACPI_CPU_DATA mAcpiCpuData; > volatile UINT32 mNumberToFinish; > MP_CPU_EXCHANGE_INFO *mExchangeInfo; > BOOLEAN mRestoreSmmConfigurationInS3 =3D FALSE; > -VOID *mGdtForAp =3D NULL; > -VOID *mIdtForAp =3D NULL; > -VOID *mMachineCheckHandlerForAp =3D NULL; > MP_MSR_LOCK *mMsrSpinLocks =3D NULL; > UINTN mMsrSpinLockCount; > UINTN mMsrCount =3D 0; > @@ -448,13 +445,6 @@ PrepareApStartupVector ( > CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN= ) > mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR)); > CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN= ) > mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR)); >=20 > - // > - // Copy AP's GDT, IDT and Machine Check handler from SMRAM to ACPI NVS > memory > - // > - CopyMem ((VOID *) mExchangeInfo->GdtrProfile.Base, mGdtForAp, > mExchangeInfo->GdtrProfile.Limit + 1); > - CopyMem ((VOID *) mExchangeInfo->IdtrProfile.Base, mIdtForAp, > mExchangeInfo->IdtrProfile.Limit + 1); > - CopyMem ((VOID *)(UINTN) mAcpiCpuData.ApMachineCheckHandlerBase, > mMachineCheckHandlerForAp, mAcpiCpuData.ApMachineCheckHandlerSize); > - > mExchangeInfo->StackStart =3D (VOID *) (UINTN) mAcpiCpuData.StackAddr= ess; > mExchangeInfo->StackSize =3D mAcpiCpuData.StackSize; > mExchangeInfo->BufferStart =3D (UINT32) StartupVector; @@ -831,6 +821,= 9 > @@ GetAcpiCpuData ( > ACPI_CPU_DATA *AcpiCpuData; > IA32_DESCRIPTOR *Gdtr; > IA32_DESCRIPTOR *Idtr; > + VOID *GdtForAp; > + VOID *IdtForAp; > + VOID *MachineCheckHandlerForAp; >=20 > if (!mAcpiS3Enable) { > return; > @@ -893,14 +886,18 @@ GetAcpiCpuData ( > Gdtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.GdtrProfile; > Idtr =3D (IA32_DESCRIPTOR *)(UINTN)mAcpiCpuData.IdtrProfile; >=20 > - mGdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + > mAcpiCpuData.ApMachineCheckHandlerSize); > - ASSERT (mGdtForAp !=3D NULL); > - mIdtForAp =3D (VOID *) ((UINTN)mGdtForAp + (Gdtr->Limit + 1)); > - mMachineCheckHandlerForAp =3D (VOID *) ((UINTN)mIdtForAp + (Idtr->Limi= t + > 1)); > + GdtForAp =3D AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + > + mAcpiCpuData.ApMachineCheckHandlerSize); > + ASSERT (GdtForAp !=3D NULL); > + IdtForAp =3D (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1)); > + MachineCheckHandlerForAp =3D (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + > + 1)); > + > + CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); CopyMem > + (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); CopyMem > + (MachineCheckHandlerForAp, (VOID > + *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, > + mAcpiCpuData.ApMachineCheckHandlerSize); >=20 > - CopyMem (mGdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); > - CopyMem (mIdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); > - CopyMem (mMachineCheckHandlerForAp, (VOID > *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, > mAcpiCpuData.ApMachineCheckHandlerSize); > + Gdtr->Base =3D (UINTN)GdtForAp; > + Idtr->Base =3D (UINTN)IdtForAp; > + mAcpiCpuData.ApMachineCheckHandlerBase =3D > + (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp; > } >=20 > /** > -- > 2.15.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel