From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A2BBE21123882 for ; Thu, 6 Sep 2018 17:26:55 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Sep 2018 17:26:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,340,1531810800"; d="scan'208";a="261408789" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga006.fm.intel.com with ESMTP; 06 Sep 2018 17:25:28 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 6 Sep 2018 17:25:27 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 6 Sep 2018 17:25:27 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.240]) with mapi id 14.03.0319.002; Fri, 7 Sep 2018 08:25:25 +0800 From: "Ni, Ruiyu" To: Nikita Leshenko , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: Liran Alon Thread-Topic: [edk2] PciBusDxe: PCI-Express bug with dynamic PcdPciExpressBaseAddress Thread-Index: AQHURhUiA1+8geIKUEK7NI30iM1IqaTj9ePA Date: Fri, 7 Sep 2018 00:25:24 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BDF99C7@SHSMSX104.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZmY5NGI4ZTMtMWUyZi00NWY1LTkzZTktNjk3MGViZTBkNTkzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiYlBFMnJOajQ3NnQ2MFwvbUMxU1E5OUdrMnBraHpGMEZCaTNQbHRieVo5UW1JMUhVR1ZmZUZ3NzFUV3hOcWJ5SG4ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: PciBusDxe: PCI-Express bug with dynamic PcdPciExpressBaseAddress X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 07 Sep 2018 00:26:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Mike, Do you think that maybe just raising to TPL_NOTIFY is enough for PCI BAR pr= obing? Though the timer interrupt still triggers, all callbacks are suspended in T= PL_NOTIFY. Thanks, Ray > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ni= kita > Leshenko > Sent: Friday, September 7, 2018 3:09 AM > To: edk2-devel@lists.01.org > Cc: Liran Alon > Subject: [edk2] PciBusDxe: PCI-Express bug with dynamic > PcdPciExpressBaseAddress >=20 > Hi, >=20 > We ran into a bug in EDK2 relating to PCI-Express in PciBusDxe. Here's th= e flow > of the bug: >=20 > 1. PciBusDxe/PciEnumeratorSupport.c: Function BarExisted probes a BAR. It > raises > TPL to TPL_HIGH_LEVEL to avoid timer interrupts while probing the BAR = and > calls PciIo->Pci.Write. > 2. BasePciExpressLib/PciExpressLib.c: The write reaches PciExpressWrite32= , > which > calls GetPciExpressBaseAddress. > 3. GetPciExpressBaseAddress retrieves the address from > PcdPciExpressBaseAddress. > 4. Reading the PCD calls DxePcdGet64 -> GetWorker -> > EfiAcquireLock(&mPcdDatabaseLock), which is at TPL_NOTIFY level. This > crashes > the firmware because step 1 raised the TPL to TPL_HIGH_LEVEL. >=20 > This doesn't happen when PcdPciExpressBaseAddress is fixed at build (beca= use > then the read is optimized to a static global variable), but when the PCD= is > dynamic PCI-Express is broken. >=20 > Does anybody have a suggestion for fixing it? >=20 > Options we thought about: > - Change mPcdDatabaseLock.Tpl to TPL_HIGH_LEVEL > - Don't use a PCD for the base address, put it in a static global variabl= e and > create functions to set and retrieve it. >=20 > Thanks, > Nikita > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel