From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D3E92095B9F6 for ; Mon, 10 Sep 2018 19:30:08 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Sep 2018 19:30:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,358,1531810800"; d="scan'208";a="88896961" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 10 Sep 2018 19:24:03 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 10 Sep 2018 19:24:03 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.143]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.16]) with mapi id 14.03.0319.002; Tue, 11 Sep 2018 10:24:00 +0800 From: "Ni, Ruiyu" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Wang, Jian J" , "Wang, Fei1" Thread-Topic: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set Thread-Index: AQHUSXO2Rts6ZkKoKk6AiFjRptr8kqTqWeWQ Date: Tue, 11 Sep 2018 02:23:24 +0000 Deferred-Delivery: Tue, 11 Sep 2018 02:24:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> References: <1536631417-39920-1-git-send-email-star.zeng@intel.com> In-Reply-To: <1536631417-39920-1-git-send-email-star.zeng@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Sep 2018 02:30:08 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: Zeng, Star > Sent: Tuesday, September 11, 2018 10:04 AM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Ni, Ruiyu ; Wan= g, > Jian J ; Wang, Fei1 > Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit i= s > set >=20 > When the HSEE in the USBCMD bit is a '1' and the HSE bit in the USBSTS > register is a '1', the xHC shall assert out-of-band error signaling to th= e host > and assert the SERR# pin. > To prevent masking any potential issues with SERR, this patch is to set > USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is > set. >=20 > Cc: Ruiyu Ni > Cc: Jian J Wang > Cc: Fei1 Wang > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 > ++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > index 5f0736a516b6..89f073e1d83f 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > @@ -587,6 +587,39 @@ XhcIsSysError ( > } >=20 > /** > + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable > Bit is set. > + > + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controll= er > Reset(HCRST). > + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is = set. > + > + @param Xhc The XHCI Instance. > + > +**/ > +VOID > +XhcSetHsee ( > + IN USB_XHCI_INSTANCE *Xhc > + ) > +{ > + EFI_STATUS Status; > + EFI_PCI_IO_PROTOCOL *PciIo; > + UINT16 XhciCmd; > + > + PciIo =3D Xhc->PciIo; > + Status =3D PciIo->Pci.Read ( > + PciIo, > + EfiPciIoWidthUint16, > + PCI_COMMAND_OFFSET, > + sizeof (XhciCmd), > + &XhciCmd > + ); > + if (!EFI_ERROR (Status)) { > + if ((XhciCmd & EFI_PCI_COMMAND_SERR) !=3D 0) { > + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > + } > + } > +} > + > +/** > Reset the XHCI host controller. >=20 > @param Xhc The XHCI Instance. > @@ -628,6 +661,14 @@ XhcResetHC ( > // > gBS->Stall (XHC_1_MILLISECOND); > Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, > XHC_USBCMD_RESET, FALSE, Timeout); > + > + if (!EFI_ERROR (Status)) { > + // > + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST. > + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. > + // > + XhcSetHsee (Xhc); > + } > } >=20 > return Status; > -- > 2.7.0.windows.1