From: "Ni, Ruiyu" <ruiyu.ni@intel.com>
To: "Zeng, Star" <star.zeng@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Wu, Hao A" <hao.a.wu@intel.com>, "Wang, Jian J" <jian.j.wang@intel.com>
Subject: Re: [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN
Date: Mon, 22 Oct 2018 08:52:07 +0000 [thread overview]
Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BEB50C2@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <1540095854-36596-2-git-send-email-star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Thanks/Ray
> -----Original Message-----
> From: Zeng, Star
> Sent: Sunday, October 21, 2018 12:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Wu,
> Hao A <hao.a.wu@intel.com>; Wang, Jian J <jian.j.wang@intel.com>
> Subject: [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision
> based on SBRN
>
> Current hard code Usb2Hc.XXXRevision may be not accurate.
> This patch updates code to assign Usb2Hc.XXXRevision based on SBRN (Serial
> Bus Release Number, PCI configuration space offset
> 0x60) although there is no code consuming them.
>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Hao Wu <hao.a.wu@intel.com>
> Cc: Jian J Wang <jian.j.wang@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Star Zeng <star.zeng@intel.com>
> ---
> MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++
> MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> index 48eccf770a35..4796d4611b19 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> @@ -1770,6 +1770,7 @@ XhcCreateUsbHc (
> EFI_STATUS Status;
> UINT32 PageSize;
> UINT16 ExtCapReg;
> + UINT8 ReleaseNumber;
>
> Xhc = AllocateZeroPool (sizeof (USB_XHCI_INSTANCE));
>
> @@ -1786,6 +1787,19 @@ XhcCreateUsbHc (
> Xhc->OriginalPciAttributes = OriginalPciAttributes;
> CopyMem (&Xhc->Usb2Hc, &gXhciUsb2HcTemplate, sizeof
> (EFI_USB2_HC_PROTOCOL));
>
> + Status = PciIo->Pci.Read (
> + PciIo,
> + EfiPciIoWidthUint8,
> + XHC_PCI_SBRN_OFFSET,
> + 1,
> + &ReleaseNumber
> + );
> +
> + if (!EFI_ERROR (Status)) {
> + Xhc->Usb2Hc.MajorRevision = (ReleaseNumber & 0xF0) >> 4;
> + Xhc->Usb2Hc.MinorRevision = (ReleaseNumber & 0x0F); }
> +
> InitializeListHead (&Xhc->AsyncIntTransfers);
>
> //
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> index 20e7ac0e8f02..feef3a4bd5ef 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> @@ -26,6 +26,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
> #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset
> #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask
>
> +#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number
> Register Offset
> +
> #define USB_HUB_CLASS_CODE 0x09
> #define USB_HUB_SUBCLASS_CODE 0x00
>
> --
> 2.7.0.windows.1
next prev parent reply other threads:[~2018-10-22 8:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-21 4:24 [PATCH 0/2] Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng
2018-10-21 4:24 ` [PATCH 1/2] MdeModulePkg XhciDxe: Assign Usb2Hc.XXXRevision based on SBRN Star Zeng
2018-10-22 8:52 ` Ni, Ruiyu [this message]
2018-10-21 4:24 ` [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Star Zeng
2018-10-22 8:52 ` Ni, Ruiyu
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