Re: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC

["Ni, Ruiyu" <ruiyu.ni@intel.com>]

Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

Thanks/Ray

> -----Original Message-----
> From: Zeng, Star
> Sent: Sunday, October 21, 2018 12:24 PM
> To: edk2-devel@lists.01.org
> Cc: Zeng, Star <star.zeng@intel.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Wu,
> Hao A <hao.a.wu@intel.com>; Wang, Jian J <jian.j.wang@intel.com>
> Subject: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field
> of PORTSC
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1267
> 
> The value 5 Port Speed field of PORTSC is new defined in
> XHCI 1.1 spec November 2017.
> 
> This patch updates XhciDxe and XhciPei to handle it, otherwise
> the USB 3.1 device may not be recognized with the XHCI controller
> following XHCI 1.1 spec November 2017.
> 
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Hao Wu <hao.a.wu@intel.com>
> Cc: Jian J Wang <jian.j.wang@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Star Zeng <star.zeng@intel.com>
> ---
>  MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c    | 4 +++-
>  MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 4 ++--
>  MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++--
>  MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 6 +++---
>  4 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> index 4796d4611b19..f1c60bef01c0 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
> @@ -403,7 +403,8 @@ XhcGetRootHubPortStatus (
>    State = XhcReadOpReg (Xhc, Offset);
> 
>    //
> -  // According to XHCI 1.0 spec, bit 10~13 of the root port status register
> identifies the speed of the attached device.
> +  // According to XHCI 1.1 spec November 2017,
> +  // bit 10~13 of the root port status register identifies the speed of the
> attached device.
>    //
>    switch ((State & XHC_PORTSC_PS) >> 10) {
>    case 2:
> @@ -415,6 +416,7 @@ XhcGetRootHubPortStatus (
>      break;
> 
>    case 4:
> +  case 5:
>      PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
>      break;
> 
> diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> index feef3a4bd5ef..ac14b7426fe7 100644
> --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
> @@ -2,7 +2,7 @@
> 
>    This file contains the register definition of XHCI host controller.
> 
> -Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions of the BSD
> License
>  which accompanies this distribution.  The full text of the license may be
> found at
> @@ -171,7 +171,7 @@ typedef union {
>  #define XHC_PORTSC_RESET                   BIT4  // Port Reset
>  #define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link
> State
>  #define XHC_PORTSC_PP                      BIT9  // Port Power
> -#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12)       // Port Speed
> +#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port
> Speed
>  #define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe
>  #define XHC_PORTSC_CSC                     BIT17 // Connect Status Change
>  #define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change
> diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
> b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
> index ee4d1f97bd04..e45da34a456e 100644
> --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
> +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c
> @@ -2,7 +2,7 @@
>  PEIM to produce gPeiUsb2HostControllerPpiGuid based on
> gPeiUsbControllerPpiGuid
>  which is used to enable recovery function from USB Drivers.
> 
> -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> 
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions
> @@ -1317,7 +1317,8 @@ XhcPeiGetRootHubPortStatus (
>    DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x
> State: %x\n", PortNumber, State));
> 
>    //
> -  // According to XHCI 1.0 spec, bit 10~13 of the root port status register
> identifies the speed of the attached device.
> +  // According to XHCI 1.1 spec November 2017,
> +  // bit 10~13 of the root port status register identifies the speed of the
> attached device.
>    //
>    switch ((State & XHC_PORTSC_PS) >> 10) {
>      case 2:
> @@ -1329,6 +1330,7 @@ XhcPeiGetRootHubPortStatus (
>        break;
> 
>      case 4:
> +    case 5:
>        PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;
>        break;
> 
> diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h
> b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h
> index 3787aeccf55f..07aeb81f2a95 100644
> --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h
> +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h
> @@ -1,7 +1,7 @@
>  /** @file
>  Private Header file for Usb Host Controller PEIM
> 
> -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
> 
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions
> @@ -82,9 +82,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
>  #define XHC_PORTSC_PED                  BIT1    // Port Enabled/Disabled
>  #define XHC_PORTSC_OCA                  BIT3    // Over-current Active
>  #define XHC_PORTSC_RESET                BIT4    // Port Reset
> -#define XHC_PORTSC_PLS                  (BIT5|BIT6|BIT7|BIT8)   // Port Link State
> +#define XHC_PORTSC_PLS                  (BIT5|BIT6|BIT7|BIT8)     // Port Link
> State
>  #define XHC_PORTSC_PP                   BIT9    // Port Power
> -#define XHC_PORTSC_PS                   (BIT10|BIT11|BIT12)     // Port Speed
> +#define XHC_PORTSC_PS                   (BIT10|BIT11|BIT12|BIT13) // Port Speed
>  #define XHC_PORTSC_LWS                  BIT16   // Port Link State Write Strobe
>  #define XHC_PORTSC_CSC                  BIT17   // Connect Status Change
>  #define XHC_PORTSC_PEC                  BIT18   // Port Enabled/Disabled Change
> --
> 2.7.0.windows.1