From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 10CCA2194D3B8 for ; Mon, 22 Oct 2018 01:53:03 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Oct 2018 01:53:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,411,1534834800"; d="scan'208";a="99562880" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 22 Oct 2018 01:53:03 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 22 Oct 2018 01:53:03 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 22 Oct 2018 01:53:02 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.21]) by shsmsx102.ccr.corp.intel.com ([169.254.2.8]) with mapi id 14.03.0319.002; Mon, 22 Oct 2018 16:53:00 +0800 From: "Ni, Ruiyu" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Wu, Hao A" , "Wang, Jian J" Thread-Topic: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC Thread-Index: AQHUaPXz3FGOsamZjEGrBJdaos4ZhqUq91Cw Date: Mon, 22 Oct 2018 08:52:07 +0000 Deferred-Delivery: Mon, 22 Oct 2018 08:53:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5BEB50C7@SHSMSX104.ccr.corp.intel.com> References: <1540095854-36596-1-git-send-email-star.zeng@intel.com> <1540095854-36596-3-git-send-email-star.zeng@intel.com> In-Reply-To: <1540095854-36596-3-git-send-email-star.zeng@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Oct 2018 08:53:04 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ruiyu Ni Thanks/Ray > -----Original Message----- > From: Zeng, Star > Sent: Sunday, October 21, 2018 12:24 PM > To: edk2-devel@lists.01.org > Cc: Zeng, Star ; Ni, Ruiyu ; Wu, > Hao A ; Wang, Jian J > Subject: [PATCH 2/2] MdeModulePkg Xhci: Handle value 5 in Port Speed fiel= d > of PORTSC >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1267 >=20 > The value 5 Port Speed field of PORTSC is new defined in > XHCI 1.1 spec November 2017. >=20 > This patch updates XhciDxe and XhciPei to handle it, otherwise > the USB 3.1 device may not be recognized with the XHCI controller > following XHCI 1.1 spec November 2017. >=20 > Cc: Ruiyu Ni > Cc: Hao Wu > Cc: Jian J Wang > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 4 +++- > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 4 ++-- > MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 6 ++++-- > MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h | 6 +++--- > 4 files changed, 12 insertions(+), 8 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > index 4796d4611b19..f1c60bef01c0 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > @@ -403,7 +403,8 @@ XhcGetRootHubPortStatus ( > State =3D XhcReadOpReg (Xhc, Offset); >=20 > // > - // According to XHCI 1.0 spec, bit 10~13 of the root port status regis= ter > identifies the speed of the attached device. > + // According to XHCI 1.1 spec November 2017, > + // bit 10~13 of the root port status register identifies the speed of = the > attached device. > // > switch ((State & XHC_PORTSC_PS) >> 10) { > case 2: > @@ -415,6 +416,7 @@ XhcGetRootHubPortStatus ( > break; >=20 > case 4: > + case 5: > PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; > break; >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > index feef3a4bd5ef..ac14b7426fe7 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > @@ -2,7 +2,7 @@ >=20 > This file contains the register definition of XHCI host controller. >=20 > -Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BS= D > License > which accompanies this distribution. The full text of the license may b= e > found at > @@ -171,7 +171,7 @@ typedef union { > #define XHC_PORTSC_RESET BIT4 // Port Reset > #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // = Port Link > State > #define XHC_PORTSC_PP BIT9 // Port Power > -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // = Port Speed > +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // = Port > Speed > #define XHC_PORTSC_LWS BIT16 // Port Link State Writ= e Strobe > #define XHC_PORTSC_CSC BIT17 // Connect Status Chang= e > #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disable= d Change > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > index ee4d1f97bd04..e45da34a456e 100644 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c > @@ -2,7 +2,7 @@ > PEIM to produce gPeiUsb2HostControllerPpiGuid based on > gPeiUsbControllerPpiGuid > which is used to enable recovery function from USB Drivers. >=20 > -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
>=20 > This program and the accompanying materials > are licensed and made available under the terms and conditions > @@ -1317,7 +1317,8 @@ XhcPeiGetRootHubPortStatus ( > DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x > State: %x\n", PortNumber, State)); >=20 > // > - // According to XHCI 1.0 spec, bit 10~13 of the root port status regis= ter > identifies the speed of the attached device. > + // According to XHCI 1.1 spec November 2017, > + // bit 10~13 of the root port status register identifies the speed of = the > attached device. > // > switch ((State & XHC_PORTSC_PS) >> 10) { > case 2: > @@ -1329,6 +1330,7 @@ XhcPeiGetRootHubPortStatus ( > break; >=20 > case 4: > + case 5: > PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; > break; >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > index 3787aeccf55f..07aeb81f2a95 100644 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciReg.h > @@ -1,7 +1,7 @@ > /** @file > Private Header file for Usb Host Controller PEIM >=20 > -Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
>=20 > This program and the accompanying materials > are licensed and made available under the terms and conditions > @@ -82,9 +82,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, EITHER EXPRESS OR IMPLIED. > #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled > #define XHC_PORTSC_OCA BIT3 // Over-current Active > #define XHC_PORTSC_RESET BIT4 // Port Reset > -#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port = Link State > +#define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Por= t Link > State > #define XHC_PORTSC_PP BIT9 // Port Power > -#define XHC_PORTSC_PS (BIT10|BIT11|BIT12) // Port = Speed > +#define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Por= t Speed > #define XHC_PORTSC_LWS BIT16 // Port Link State Write= Strobe > #define XHC_PORTSC_CSC BIT17 // Connect Status Change > #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled= Change > -- > 2.7.0.windows.1