From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Thu, 25 Apr 2019 11:07:35 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 11:07:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,394,1549958400"; d="scan'208";a="143611984" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga008.fm.intel.com with ESMTP; 25 Apr 2019 11:07:34 -0700 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 25 Apr 2019 11:07:34 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 25 Apr 2019 11:07:33 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.92]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.42]) with mapi id 14.03.0415.000; Fri, 26 Apr 2019 02:07:32 +0800 From: "Ni, Ray" To: "Kinney, Michael D" , "devel@edk2.groups.io" CC: "Dong, Eric" , Laszlo Ersek Subject: Re: [Patch 2/4] UefiCpuPkg/MpInitLib: Avoid MSR_IA32_APIC_BASE for single core Thread-Topic: [Patch 2/4] UefiCpuPkg/MpInitLib: Avoid MSR_IA32_APIC_BASE for single core Thread-Index: AQHU+4/R76OFFGYJC06ABc3t1q3VCaZNLBjQ Date: Thu, 25 Apr 2019 18:07:29 +0000 Deferred-Delivery: Thu, 25 Apr 2019 18:07:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C104B05@SHSMSX104.ccr.corp.intel.com> References: <20190425175334.5944-1-michael.d.kinney@intel.com> <20190425175334.5944-3-michael.d.kinney@intel.com> In-Reply-To: <20190425175334.5944-3-michael.d.kinney@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDlhMzFhYzUtMDRiMi00ZTAwLTliODctYWMxYWI1N2Q0YmU3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiTTBkNFVmNUg4VEd5d1QrRXBFdVpLelJwczJyV2tmbG5qZFJmZVlWS3NscVBHU0lYOE40OElRQldyR1NiaExCWCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Kinney, Michael D > Sent: Thursday, April 25, 2019 10:54 AM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Laszlo > Ersek > Subject: [Patch 2/4] UefiCpuPkg/MpInitLib: Avoid MSR_IA32_APIC_BASE for > single core >=20 > Avoid access to MSR_IA32_APIC_BASE that may not be supported > on single core CPUs. If PcdCpuMaxLogicalProcessorNumber is 1, > then there is only one CPU that must be the BSP. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Signed-off-by: Michael D Kinney > --- > UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > index 35dff91fd2..5488049c08 100644 > --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > @@ -1,7 +1,7 @@ > /** @file > MP initialize support functions for PEI phase. >=20 > - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -101,6 +101,19 @@ GetCpuMpData ( > MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; > IA32_DESCRIPTOR Idtr; >=20 > + // > + // If there is only 1 CPU, then it must be the BSP. This avoids an ac= cess to > + // MSR_IA32_APIC_BASE that may not be supported on single core CPUs. > + // > + if (PcdGet32 (PcdCpuMaxLogicalProcessorNumber) =3D=3D 1) { > + CpuMpData =3D GetCpuMpDataFromGuidedHob (); > + ASSERT (CpuMpData !=3D NULL); > + return CpuMpData; > + } > + > + // > + // Otherwise use MSR_IA32_APIC_BASE to determine if the CPU is BSP or > AP. > + // > ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > if (ApicBaseMsr.Bits.BSP =3D=3D 1) { > CpuMpData =3D GetCpuMpDataFromGuidedHob (); > -- > 2.21.0.windows.1