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 Tue, 11 Jun 2019 10:11:24 +0800
From: "Ni, Ray" <ray.ni@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "Desimone, Nathaniel L"
	<nathaniel.l.desimone@intel.com>, "Chiu, Chasel" <chasel.chiu@intel.com>
CC: "Kubacki, Michael A" <michael.a.kubacki@intel.com>, "Chaganty, Rangasai V"
	<rangasai.v.chaganty@intel.com>
Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
Thread-Topic: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support
 DefaultPolicyInit PPI.
Thread-Index: AQHVGiv+onCNmePPk0Si+z9kkhHGkKaN3j4AgACTqlA=
Date: Tue, 11 Jun 2019 02:11:24 +0000
Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C19FDDC@SHSMSX104.ccr.corp.intel.com>
References: <20190603164658.4668-1-chasel.chiu@intel.com>
 <20190603164658.4668-2-chasel.chiu@intel.com>
 <02A34F284D1DA44BB705E61F7180EF0AAEBD5DA3@ORSMSX114.amr.corp.intel.com>
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Chasel,
Where is the code that produces DefaultPolicyInit PPI?
Is the code public available?

And in general, I think the patch consists of several changes:
1. change version compare from "=3D=3D" to ">=3D" to support FSP be used i=
n newer board.
2. Add definition of SiDefaultPolicyPpi
3. Update non-FSP version of PeiSiliconPolicyInitLib to consume the SiDefa=
ultPolicyPpi
4. Update config block for GFX
5. Add SiXXXInstallPolicyReadyPpi
6. maybe more....

Can you please try to separate the changes to small patches?

Regarding to the changes in KabylakeSiliconPkg\Library\PeiSiPolicyLib\PeiS=
iPolicyLibPreMem.c:
There are two APIs: SiPreMemInstallPolicyPpi and SiPreMemInstallPolicyRead=
yPpi.

When FSP runs in API mode, the calling flow is as below:
FspWrapperPeim::PeiMemoryDiscoveredNotify
--> MinPlatformPkg/../PeiFspWrapperPlatformLib::UpdateFspsUpdData
    --> KabylakeSiliconPkg/.../SiliconPolicyInitPostMem
        --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiCreateConfigBlocks
        --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiInstallPolicyPpi

Do you think that it's possible to update KabylakeSiliconPkg/.../SiliconPo=
licyInitPostMem() to
call SiDefaultPolicyInitPpi->PeiPolicyInit()? To align the behavior when F=
SP runs in dispatch mode.

Thanks,
Ray

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate
> DeSimone
> Sent: Thursday, June 6, 2019 5:44 PM
> To: Chiu, Chasel <chasel.chiu@intel.com>; devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Chaganty, Rangasai=
 V
> <rangasai.v.chaganty@intel.com>
> Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support
> DefaultPolicyInit PPI.
>=20
> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
>=20
> -----Original Message-----
> From: Chiu, Chasel
> Sent: Monday, June 3, 2019 9:47 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>
> Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI.
>=20
> From: "Chasel, Chiu" <chasel.chiu@intel.com>
>=20
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1870
>=20
> FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loader =
to
> consume and install policy with default settings built-in by FSP.
> Boot loader then may patch policy with per-board settings and then insta=
ll
> PolicyReady PPI to start silicon initialization (policy consumer code)
>=20
> Since different version FSP has different version policy structure, the =
policy
> revision check code has been extended to support newer revision policy a=
nd
> the policy structure boot loader consuming has been aligned with the sam=
e
> structure inside FSP.
> (FSP will maintain policy structure backward
> compatibility)
>=20
> Also removed microcode location searching code from silicon scope becaus=
e
> silicon code should not access hard-coded flash region unconditionally.
> This should be done by platform/boot loader side.
>=20
> Cc: Michael A Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> ---
>=20
> Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic=
yLi
> b.c                                                      | 133 +++++++--=
--------------------------------------
> ------------------------------------------------------------------------=
--------------
>  Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.=
c
> |  53 ++++++++++++++++++++++++++++++++++++++++++++++++-----
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPr=
eMem
> .c                                                      |  50
> ++++++++++++++++++++++++++++++++++++++++++++++----
>  Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPol=
icyInit.c
> |  32 +++++++++++++++++++++++++-------
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPoli=
cyInitPr
> eMem.c                                              |  39 ++++++++++++++=
+++++++++++++-------
> -----
>=20
> Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi=
b.
> c                                                         |   6 +++---
>=20
> Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS=
a
> PolicyLib.c                                                |   4 ++--
>=20
> Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPr=
int
> Policy.c                                                 |  14 +++++++--=
-----
>  Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> |   4 +++-
>=20
> Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic=
yLi
> brary.h                                                  |   4 +---
>  Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
> |  32 ++++++++++++++++++++++++++++----
>=20
> Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyIni=
t.h
> |  36 ++++++++++++++++++++++++++++++++++++
>  Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
> |  36 ++++++++++++++++++++++++++++++++++++
>  Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.=
inf
> |   8 +++++---
>  Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPol=
icyInit.h
> |   4 +++-
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPost=
MemSi
> liconPolicyInitLib.inf                                 |  75
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiSil=
iconPoli
> cyInitLib.inf =3D> PeiPreMemSiliconPolicyInitLib.inf} |  11 ++++++++---
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiS=
iliconP
> olicyInitLibFsp.inf                                  |   5 +++--
>=20
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiS=
iliconP
> olicyInitLibFspAml.inf                               |   1 +
>  Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> |   4 ++++
>=20
> Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic=
s
> PeiConfig.h                                                |  16 +++++++=
+++++++--
>=20
> Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS=
aP
> olicyLib.inf                                              |   3 ++-
>  22 files changed, 384 insertions(+), 186 deletions(-)
>=20
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Lib.c
> b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Lib.c
> index cb7f379e0f..eb83cd4918 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Lib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp
> +++ uPolicyLib.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file is PeiCpuPolicy library.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
> #include <Library/ConfigBlockLib.h>  #include <Library/PostCodeLib.h>
>=20
> -#ifndef FSP_FLAG
> -/**
> -  Get the next microcode patch pointer.
> -
> -  @param[in, out] MicrocodeData - Input is a pointer to the last microc=
ode
> patch address found,
> -                                  and output points to the next patch a=
ddress found.
> -
> -  @retval EFI_SUCCESS           - Patch found.
> -  @retval EFI_NOT_FOUND         - Patch not found.
> -**/
> -EFI_STATUS
> -EFIAPI
> -RetrieveMicrocode (
> -  IN OUT CPU_MICROCODE_HEADER **MicrocodeData
> -  )
> -{
> -  UINTN                MicrocodeStart;
> -  UINTN                MicrocodeEnd;
> -  UINTN                TotalSize;
> -
> -  if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGe=
t32
> (PcdFlashMicrocodeFvSize) =3D=3D 0)) {
> -    return EFI_NOT_FOUND;
> -  }
> -
> -  ///
> -  /// Microcode binary in SEC
> -  ///
> -  MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
> -          ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32
> (PcdFlashMicrocodeFvBase))->HeaderLength +
> -          sizeof (EFI_FFS_FILE_HEADER);
> -
> -  MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
> (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
> -
> -  if (*MicrocodeData =3D=3D NULL) {
> -    *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN)
> MicrocodeStart;
> -  } else {
> -    if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN)
> MicrocodeStart) {
> -      DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart
> \n"));
> -      return EFI_NOT_FOUND;
> -    }
> -
> -    TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize);
> -    if (TotalSize =3D=3D 0) {
> -      TotalSize =3D 2048;
> -    }
> -
> -    *MicrocodeData =3D (CPU_MICROCODE_HEADER *)
> ((UINTN)*MicrocodeData + TotalSize);
> -    if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN)
> (MicrocodeEnd) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) {
> -      DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd
> \n"));
> -      return EFI_NOT_FOUND;
> -    }
> -  }
> -  return EFI_SUCCESS;
> -}
> -
> -/**
> -  Get the microcode patch pointer.
> -
> -  @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NUL=
L
> if not found.
> -**/
> -EFI_PHYSICAL_ADDRESS
> -PlatformCpuLocateMicrocodePatch (
> -  VOID
> -  )
> -{
> -  EFI_STATUS           Status;
> -  CPU_MICROCODE_HEADER *MicrocodeData;
> -  EFI_CPUID_REGISTER   Cpuid;
> -  UINT32               UcodeRevision;
> -  UINTN                MicrocodeBufferSize;
> -  VOID                 *MicrocodeBuffer =3D NULL;
> -
> -  AsmCpuid (
> -    CPUID_VERSION_INFO,
> -    &Cpuid.RegEax,
> -    &Cpuid.RegEbx,
> -    &Cpuid.RegEcx,
> -    &Cpuid.RegEdx
> -    );
> -
> -  UcodeRevision =3D GetCpuUcodeRevision ();
> -  MicrocodeData =3D NULL;
> -  while (TRUE) {
> -    ///
> -    /// Find the next patch address
> -    ///
> -    Status =3D RetrieveMicrocode (&MicrocodeData);
> -    DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData));
> -
> -    if (Status !=3D EFI_SUCCESS) {
> -      break;
> -    } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData,
> &UcodeRevision)) {
> -      break;
> -    }
> -  }
> -
> -  if (EFI_ERROR (Status)) {
> -    return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
> -  }
> -
> -  ///
> -  /// Check that microcode patch size is <=3D 128K max size,
> -  /// then copy the patch from FV to temp buffer for faster access.
> -  ///
> -  MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize;
> -
> -  if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) {
> -    MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES
> (MicrocodeBufferSize));
> -    if (MicrocodeBuffer !=3D NULL) {
> -      DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
> -      CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
> -
> -      return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
> -    } else {
> -      DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for
> Microcode Patch.\n"));
> -    }
> -  } else {
> -    DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max
> allowed size of 128K.\n"));
> -  }
> -  return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif
>=20
>  /**
>    Load Config block default
> @@ -158,9 +36,12 @@ LoadCpuConfigDefault (
>    CpuConfig->AesEnable             =3D CPU_FEATURE_ENABLE;
>    CpuConfig->EnableRsr             =3D CPU_FEATURE_ENABLE;
>    CpuConfig->SmmbaseSwSmiNumber    =3D (UINTN) PcdGet8
> (PcdSmmbaseSwSmi);
> -#ifndef FSP_FLAG
> -  CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch
> (); -#endif
> +  //
> +  // This function is shared by both non-FSP and FSP scenarios and alwa=
ys
> executed unconditionally.
> +  // Since FSP/silicon code should not unconditionally access any
> + hardcoding flash regions (that region might not be accessible  // in
> unknown platforms), the microcode location searching code should be
> moved to outside silicon code scope.
> +  //
> +  CpuConfig->MicrocodePatchAddress =3D 0;
>  }
>=20
>=20
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
.c
> index 813b868fcf..c3a8bbf539 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic=
yLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic
> +++ yLib.c
> @@ -2,7 +2,7 @@
>    This file is PeiSiPolicyLib library creates default settings of RC
>    Policy and installs RC Policy PPI.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -196,8 +196,6 @@ DumpSiPolicy (
>=20
>  /**
>    SiInstallPolicyPpi installs SiPolicyPpi.
> -  While installed, RC assumes the Policy is ready and finalized. So ple=
ase
> update and override
> -  any setting before calling this function.
>=20
>    @param[in] SiPolicyPpi         The pointer to Silicon Policy PPI inst=
ance
>=20
> @@ -226,11 +224,56 @@ SiInstallPolicyPpi (
>    Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOI=
D *)
> &SiConfig);
>    ASSERT_EFI_ERROR (Status);
>=20
> +  //
> +  // Install Silicon Policy PPI
> +  //
> +  Status =3D PeiServicesInstallPpi (SiPolicyPpiDesc);
> +  ASSERT_EFI_ERROR (Status);
> +  return Status;
> +}
> +
> +/**
> +  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
> +  While installed, RC assumes the Policy is ready and finalized. So
> +please update and override
> +  any setting before calling this function.
> +
> +  @retval EFI_SUCCESS            The policy is installed.
> +  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffe=
r
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiInstallPolicyReadyPpi (
> +  VOID
> +  )
> +{
> +  EFI_STATUS             Status;
> +  EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc;
> +  SI_POLICY_PPI          *SiPolicy;
> +
> +  SiPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (size=
of
> + (EFI_PEI_PPI_DESCRIPTOR));  if (SiPolicyPpiDesc =3D=3D NULL) {
> +    ASSERT (FALSE);
> +    return EFI_OUT_OF_RESOURCES;
> +  }
> +
> +  SiPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI |
> + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> +  SiPolicyPpiDesc->Guid  =3D &gSiPolicyReadyPpiGuid;
> +  SiPolicyPpiDesc->Ppi   =3D NULL;
> +
> +  SiPolicy =3D NULL;
> +  Status =3D PeiServicesLocatePpi (
> +             &gSiPolicyPpiGuid,
> +             0,
> +             NULL,
> +             (VOID **)&SiPolicy
> +             );
> +  ASSERT_EFI_ERROR(Status);
> +
>    DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n"));
> -  DumpSiPolicy (SiPolicyPpi);
> +  DumpSiPolicy (SiPolicy);
>=20
>    //
> -  // Install Silicon Policy PPI
> +  // Install Silicon Policy Ready PPI
>    //
>    Status =3D PeiServicesInstallPpi (SiPolicyPpiDesc);
>    ASSERT_EFI_ERROR (Status);
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
PreMe
> m.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
PreMe
> m.c
> index e0d83cb467..e6506a0445 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
PreMe
> m.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic
> +++ yLibPreMem.c
> @@ -2,7 +2,7 @@
>    This file is PeiSiPolicyLib library creates default settings of RC
>    Policy and installs RC Policy PPI.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks (
>=20
>  /**
>    SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
> -  While installed, RC assumes the Policy is ready and finalized. So ple=
ase
> update and override
> -  any setting before calling this function.
>=20
>    @param[in] SiPreMemPolicyPpi   The pointer to Silicon Policy PPI inst=
ance
>=20
> @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi (
>    SiPolicyPreMemPpiDesc->Ppi   =3D SiPolicyPreMemPpi;
>=20
>    //
> +  // Install Silicon Policy PPI
> +  //
> +  Status =3D PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
> +  ASSERT_EFI_ERROR (Status);
> +  return Status;
> +}
> +
> +/**
> +  SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
> +  While installed, RC assumes the Policy is ready and finalized. So
> +please update and override
> +  any setting before calling this function.
> +
> +  @retval EFI_SUCCESS            The policy is installed.
> +  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffe=
r
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiPreMemInstallPolicyReadyPpi (
> +  VOID
> +  )
> +{
> +  EFI_STATUS             Status;
> +  EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc;
> +  SI_PREMEM_POLICY_PPI    *SiPolicyPreMemPpi;
> +
> +  SiPolicyPreMemPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
> + (sizeof (EFI_PEI_PPI_DESCRIPTOR));  if (SiPolicyPreMemPpiDesc =3D=3D N=
ULL) {
> +    ASSERT (FALSE);
> +    return EFI_OUT_OF_RESOURCES;
> +  }
> +
> +  SiPolicyPreMemPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI |
> + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
> +  SiPolicyPreMemPpiDesc->Guid  =3D &gSiPreMemPolicyReadyPpiGuid;
> +  SiPolicyPreMemPpiDesc->Ppi   =3D NULL;
> +
> +  Status =3D PeiServicesLocatePpi (
> +             &gSiPreMemPolicyPpiGuid,
> +             0,
> +             NULL,
> +             (VOID **)&SiPolicyPreMemPpi
> +             );
> +  ASSERT_EFI_ERROR (Status);
> +
> +  //
>    // Print whole PCH_POLICY_PPI and serial out.
>    //
>    PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@
> SiPreMemInstallPolicyPpi (
>    CpuPreMemPrintPolicy (SiPolicyPreMemPpi);
>=20
>    //
> -  // Install Silicon Policy PPI
> +  // Install PreMem Silicon Policy Ready PPI
>    //
>    Status =3D PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
>    ASSERT_EFI_ERROR (Status);
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .c
> index 0de415ad19..6cbc39c29e 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P
> +++ eiPolicyInit.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file is SampleCode for Intel PEI Platform Policy initialization.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem (
>    IN OUT VOID *Policy
>    )
>  {
> -  EFI_STATUS                   Status;
> -  SI_POLICY_PPI                *SiPolicyPpi;
> +  EFI_STATUS                            Status;
> +  SI_POLICY_PPI                         *SiPolicyPpi;
> +  PEI_SI_DEFAULT_POLICY_INIT_PPI        *PeiSiDefaultPolicyInitPpi;
>=20
>    DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Post-
> Memory...\n"));
>=20
>    ASSERT (Policy =3D=3D NULL);
>=20
>    //
> -  // Call SiCreateConfigBlocks to initialize Silicon Policy structure
> -  // and get all Intel default policy settings.
> +  // Locate Policy init PPI to install default silicon policy
>    //
> -  Status =3D SiCreateConfigBlocks (&SiPolicyPpi);
> +  Status =3D PeiServicesLocatePpi (
> +             &gSiDefaultPolicyInitPpiGuid,
> +             0,
> +             NULL,
> +             (VOID **) &PeiSiDefaultPolicyInitPpi
> +             );
>    ASSERT_EFI_ERROR (Status);
> +  if (PeiSiDefaultPolicyInitPpi !=3D NULL) {
> +    Status =3D PeiSiDefaultPolicyInitPpi->PeiPolicyInit ();
> +    ASSERT_EFI_ERROR (Status);
> +    if (Status =3D=3D EFI_SUCCESS) {
> +      Status =3D PeiServicesLocatePpi (
> +                 &gSiPolicyPpiGuid,
> +                 0,
> +                 NULL,
> +                 (VOID **) &SiPolicyPpi
> +                 );
> +      ASSERT_EFI_ERROR (Status);
> +    }
> +  }
>=20
>    return SiPolicyPpi;
>  }
> @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem (
>    // While installed, RC assumes the Policy is ready and finalized. So =
please
>    // update and override any setting before calling this function.
>    //
> -  Status =3D SiInstallPolicyPpi (SiPolicyPpi);
> +  Status =3D SiInstallPolicyReadyPpi ();
>    ASSERT_EFI_ERROR (Status);
>=20
>    DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post-
> Memory\n")); diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> PreMem.c
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> PreMem.c
> index fd76b4fac3..8e138b1eb2 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> PreMem.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P
> +++ eiPolicyInitPreMem.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file is SampleCode for Intel PEI Platform Policy initialization.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem (
>    IN OUT VOID *Policy
>    )
>  {
> -  EFI_STATUS                   Status;
> -  SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi;
> +  EFI_STATUS                            Status;
> +  SI_PREMEM_POLICY_PPI                  *SiPreMemPolicyPpi;
> +  PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
> + *PeiPreMemSiDefaultPolicyInitPpi;
>=20
>    DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-
> Memory...\n"));
>=20
>    ASSERT (Policy =3D=3D NULL);
> +  SiPreMemPolicyPpi =3D NULL;
>=20
>    //
> -  // Call SiCreatePreMemConfigBlocks to initialize platform policy stru=
cture
> -  // and get all intel default policy settings.
> +  // Locate Policy init PPI to install default silicon policy
>    //
> -  Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
> +  Status =3D PeiServicesLocatePpi (
> +             &gSiPreMemDefaultPolicyInitPpiGuid,
> +             0,
> +             NULL,
> +             (VOID **) &PeiPreMemSiDefaultPolicyInitPpi
> +             );
>    ASSERT_EFI_ERROR (Status);
> -
> +  if (PeiPreMemSiDefaultPolicyInitPpi !=3D NULL) {
> +    Status =3D PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();
> +    ASSERT_EFI_ERROR (Status);
> +    if (Status =3D=3D EFI_SUCCESS) {
> +      Status =3D PeiServicesLocatePpi (
> +                 &gSiPreMemPolicyPpiGuid,
> +                 0,
> +                 NULL,
> +                 (VOID **) &SiPreMemPolicyPpi
> +                 );
> +      ASSERT_EFI_ERROR (Status);
> +    }
> +  }
>    return SiPreMemPolicyPpi;
>  }
>=20
> @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem (
>    )
>  {
>    EFI_STATUS                   Status;
> -  SI_PREMEM_POLICY_PPI         *SiPreMemPolicyPpi;
> -
> -  SiPreMemPolicyPpi =3D Policy;
>=20
>    //
> -  // Install SiPreMemPolicyPpi.
> +  // Install Policy Ready PPI
>    // While installed, RC assumes the Policy is ready and finalized. So =
please
>    // update and override any setting before calling this function.
>    //
> -  Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
> +  Status =3D SiPreMemInstallPolicyReadyPpi ();
>    ASSERT_EFI_ERROR (Status);
>=20
>    DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-
> Memory\n")); diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy=
Li
> b.c
> b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy=
Li
> b.c
> index 31c7d59d1d..803de0999e 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy=
Li
> b.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePo
> +++ licyLib.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file is PeiMePolicy library.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig (
>    DEBUG_CODE_BEGIN ();
>    DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG --
> ---------------\n"));
>    DEBUG ((DEBUG_INFO, " Revision                  : 0x%x\n",
> MePeiPreMemConfig->Header.Revision));
> -  ASSERT (MePeiPreMemConfig->Header.Revision =3D=3D
> ME_PEI_PREMEM_CONFIG_REVISION);
> +  ASSERT (MePeiPreMemConfig->Header.Revision >=3D
> + ME_PEI_PREMEM_CONFIG_REVISION);
>=20
>    DEBUG ((DEBUG_INFO, " HeciTimeouts              : 0x%x\n",
> MePeiPreMemConfig->HeciTimeouts));
>    DEBUG ((DEBUG_INFO, " DidInitStat               : 0x%x\n",
> MePeiPreMemConfig->DidInitStat));
> @@ -129,7 +129,7 @@ PrintMePeiConfig (
>    DEBUG_CODE_BEGIN ();
>    DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG ---------=
------
> --\n"));
>    DEBUG ((DEBUG_INFO, " Revision                  : 0x%x\n", MePeiConfi=
g-
> >Header.Revision));
> -  ASSERT (MePeiConfig->Header.Revision =3D=3D ME_PEI_CONFIG_REVISION);
> +  ASSERT (MePeiConfig->Header.Revision >=3D ME_PEI_CONFIG_REVISION);
>=20
>    DEBUG ((DEBUG_INFO, " EndOfPostMessage          : 0x%x\n", MePeiConfi=
g-
> >EndOfPostMessage));
>    DEBUG ((DEBUG_INFO, " Heci3Enabled              : 0x%x\n", MePeiConfi=
g-
> >Heci3Enabled));
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx=
e
> SaPolicyLib.c
> b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx=
e
> SaPolicyLib.c
> index 67fe214d0e..be36468b1e 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx=
e
> SaPolicyLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLi
> +++ b/DxeSaPolicyLib.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file provide services for DXE phase policy default initializatio=
n
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -38,7 +38,7 @@ SaPrintPolicyProtocol (
>=20
>    DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print=
 BEGIN
> -----------------\n"));
>    DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy-
> >TableHeader.Header.Revision));
> -  ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D
> SA_POLICY_PROTOCOL_REVISION);
> +  ASSERT (SaPolicy->TableHeader.Header.Revision >=3D
> + SA_POLICY_PROTOCOL_REVISION);
>    DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -=
-
> ---------------\n"));
>    DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig-
> >EnableAbove4GBMmio));
>    DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print=
 END ---
> --------------\n")); diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Sa=
Pri
> ntPolicy.c
> b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Sa=
Pri
> ntPolicy.c
> index 8b3a81a1c4..5c80fca88e 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Sa=
Pri
> ntPolicy.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi
> +++ b/SaPrintPolicy.c
> @@ -1,7 +1,7 @@
>  /** @file
>    This file provides service for PEI phase policy printing
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem (
>=20
>    DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem=
)
> Print BEGIN -----------------\n"));
>    DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi-
> >TableHeader.Header.Revision));
> -  ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision =3D=3D
> SI_PREMEM_POLICY_REVISION);
> +  ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >=3D
> + SI_PREMEM_POLICY_REVISION);
>=20
>    DEBUG ((DEBUG_INFO, "------------------------
> SA_MISC_PEI_PREMEM_CONFIG  -----------------\n"));
>    DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig-
> >Header.Revision));
> -  ASSERT (MiscPeiPreMemConfig->Header.Revision =3D=3D
> SA_MISC_PEI_PREMEM_CONFIG_REVISION);
> +  ASSERT (MiscPeiPreMemConfig->Header.Revision >=3D
> + SA_MISC_PEI_PREMEM_CONFIG_REVISION);
>    DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :",
> SA_MC_MAX_SOCKETS));
>    for (Index =3D 0; Index < SA_MC_MAX_SOCKETS; Index++) {
>      DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig-
> >SpdAddressTable[Index]));
> @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem (
>    DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ---------=
----
> -----------------\n"));
>    DEBUG ((DEBUG_INFO, " Guid                : %g\n", &MemConfig-
> >Header.GuidHob.Name));
>    DEBUG ((DEBUG_INFO, " Revision            : %d\n",   MemConfig-
> >Header.Revision));
> -  ASSERT (MemConfig->Header.Revision =3D=3D MEMORY_CONFIG_REVISION);
> +  ASSERT (MemConfig->Header.Revision >=3D MEMORY_CONFIG_REVISION);
>    DEBUG ((DEBUG_INFO, " Size                : 0x%x\n", MemConfig-
> >Header.GuidHob.Header.HobLength));
>    DEBUG ((DEBUG_INFO, " HobBufferSize       : 0x%x\n", MemConfig-
> >HobBufferSize));
>    DEBUG ((DEBUG_INFO, " EccSupport          : 0x%x\n", MemConfig-
> >EccSupport));
> @@ -296,17 +296,17 @@ SaPrintPolicyPpi (
>=20
>    DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print=
 BEGIN -
> ----------------\n"));
>    DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi-
> >TableHeader.Header.Revision));
> -  ASSERT (SiPolicyPpi->TableHeader.Header.Revision =3D=3D
> SI_POLICY_REVISION);
> +  ASSERT (SiPolicyPpi->TableHeader.Header.Revision >=3D
> + SI_POLICY_REVISION);
>    DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG ---=
----
> ----------\n"));
>    DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision));
> -  ASSERT (GtConfig->Header.Revision =3D=3D
> GRAPHICS_PEI_CONFIG_REVISION);
> +  ASSERT (GtConfig->Header.Revision >=3D
> GRAPHICS_PEI_CONFIG_REVISION);
>    DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig-
> >PeiGraphicsPeimInit));
>    DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr));
>    DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize));
>    DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig-
> >GraphicsConfigPtr));
>    DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG ------------=
-----
> \n"));
>    DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision));
> -  ASSERT (Vtd->Header.Revision =3D=3D VTD_CONFIG_REVISION);
> +  ASSERT (Vtd->Header.Revision >=3D VTD_CONFIG_REVISION);
>    DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable));
>    DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut));
>    DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :",
> SA_VTD_ENGINE_NUMBER)); diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> index 2dc7be45d2..aa88e761b8 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h
> @@ -1,7 +1,7 @@
>  /** @file
>    This file declares various data structures used in CPU reference code=
.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
>  #define CPU_CAUSE_BY_ASSOCIATION    0x0100
>  #define CPU_CAUSE_UNSPECIFIED       0x8000
>=20
> +#define MAX_MICROCODE_PATCH_SIZE    0x20000
> +
>  typedef UINT32 CPU_STATE_CHANGE_CAUSE;
>=20
>  ///
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Library.h
> b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Library.h
> index d2a475591d..23321d6432 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol=
icy
> Library.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCp
> +++ uPolicyLibrary.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Header file for the PeiCpuPolicyLib library.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent  #include
> <Register/Cpuid.h>  #include <Library/PcdLib.h>
>=20
> -#define MAX_MICROCODE_PATCH_SIZE 0x20000
> -
>  #endif // _PEI_CPU_POLICY_LIBRARY_H_
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLi=
b.h
> b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
> index 7bd26863b5..2c0387f678 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Prototype of the SiPolicyLib library.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -65,8 +65,6 @@ SiCreateConfigBlocks (
>=20
>  /**
>    SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
> -  While installed, RC assumes the Policy is ready and finalized. So ple=
ase
> update and override
> -  any setting before calling this function.
>=20
>    @param[in] SiPreMemPolicyPpi   The pointer to Silicon PREMEM Policy P=
PI
> instance
>=20
> @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi (
>    );
>=20
>  /**
> -  SiInstallPolicyPpi installs SiPolicyPpi.
> +  SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
>    While installed, RC assumes the Policy is ready and finalized. So ple=
ase
> update and override
>    any setting before calling this function.
>=20
> +  @retval EFI_SUCCESS            The policy is installed.
> +  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffe=
r
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiPreMemInstallPolicyReadyPpi (
> +  VOID
> +  );
> +
> +/**
> +  SiInstallPolicyPpi installs SiPolicyPpi.
> +
>    @param[in] SiPolicyPpi         The pointer to Silicon Policy PPI inst=
ance
>=20
>    @retval EFI_SUCCESS            The policy is installed.
> @@ -96,6 +106,20 @@ SiInstallPolicyPpi (
>    );
>=20
>  /**
> +  SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
> +  While installed, RC assumes the Policy is ready and finalized. So
> + please update and override  any setting before calling this function.
> +
> +  @retval EFI_SUCCESS            The policy is installed.
> +  @retval EFI_OUT_OF_RESOURCES   Insufficient resources to create buffe=
r
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiInstallPolicyReadyPpi (
> +  VOID
> +  );
> +
> +/**
>    Print out all silicon policy information.
>=20
>    @param[in] SiPolicyPpi         The pointer to Silicon Policy PPI inst=
ance
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyI=
ni
> t.h
> b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyI=
ni
> t.h
> new file mode 100644
> index 0000000000..b8a526b9b7
> --- /dev/null
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPol
> +++ icyInit.h
> @@ -0,0 +1,36 @@
> +/** @file
> +  This file defines the PPI function for installing PreMem silicon
> +policy
> +  PPI with default settings.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
> +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
> +
> +//
> +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
> +//
> +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
> +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
> +
> +/**
> +  Initialize and install default silicon policy PPI **/ typedef
> +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) (
> +  VOID
> +  );
> +
> +///
> +/// This PPI provides function to install default silicon policy ///
> +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
> +  PEI_PREMEM_POLICY_INIT   PeiPreMemPolicyInit;
> +};
> +
> +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
> +
> +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
> b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h
> new file mode 100644
> index 0000000000..d620cf29d4
> --- /dev/null
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyIni
> +++ t.h
> @@ -0,0 +1,36 @@
> +/** @file
> +  This file defines the PPI function for installing PostMem silicon
> +policy
> +  PPI with default settings.
> +
> +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
> +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
> +
> +//
> +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
> +//
> +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI
> +PEI_SI_DEFAULT_POLICY_INIT_PPI;
> +
> +/**
> +  Initialize and install default silicon policy PPI **/ typedef
> +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) (
> +  VOID
> +  );
> +
> +///
> +/// This PPI provides function to install default silicon policy ///
> +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
> +  PEI_POLICY_INIT   PeiPolicyInit;
> +};
> +
> +extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
> +
> +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib=
.inf
> index 1d992cfbbd..47f58d16e9 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic=
yLib.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolic
> +++ yLib.inf
> @@ -1,7 +1,7 @@
>  ## @file
>  # Component description file for the PeiSiPolicyLib library.
>  #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  #
> @@ -49,8 +49,10 @@ gSiConfigGuid        ## CONSUMES
>=20
>=20
>  [Ppis]
> -gSiPolicyPpiGuid       ## PRODUCES
> -gSiPreMemPolicyPpiGuid ## PRODUCES
> +gSiPolicyPpiGuid            ## PRODUCES
> +gSiPreMemPolicyPpiGuid      ## PRODUCES
> +gSiPreMemPolicyReadyPpiGuid ## PRODUCES
> +gSiPolicyReadyPpiGuid       ## PRODUCES
>=20
>  [Pcd]
>  gSiPkgTokenSpaceGuid.PcdSiCsmEnable  ## CONSUMES diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .h
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .h
> index c38294cfbe..f2fecee8c6 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
licyInit
> .h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P
> +++ eiPolicyInit.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Header file for the PolicyInitPei PEIM.
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent  #include
> <PiPei.h>  #include <Library/DebugLib.h>  #include
> <Library/MemoryAllocationLib.h>
> +#include <Ppi/PeiPreMemSiDefaultPolicyInit.h>
> +#include <Ppi/PeiSiDefaultPolicyInit.h>
>=20
>  #include "PeiSiPolicyInit.h"
>=20
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
stMe
> mSiliconPolicyInitLib.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo=
stMe
> mSiliconPolicyInitLib.inf
> new file mode 100644
> index 0000000000..83c909e681
> --- /dev/null
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P
> +++ eiPostMemSiliconPolicyInitLib.inf
> @@ -0,0 +1,75 @@
> +## @file
> +# Library functions for Policy Initialization Library.
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> # #
> +SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +#########################################################
> ##############
> +#########
> +#
> +# Defines Section - statements that will be processed to create a Makef=
ile.
> +#
> +#########################################################
> ##############
> +#########
> +[Defines]
> +  INF_VERSION                    =3D 0x00010005
> +  BASE_NAME                      =3D PeiPostMemSiliconPolicyInitLib
> +  FILE_GUID                      =3D FA0795E2-BCB3-4627-9FB3-A325548658=
B4
> +  MODULE_TYPE                    =3D BASE
> +  VERSION_STRING                 =3D 1.0
> +  LIBRARY_CLASS                  =3D SiliconPolicyInitLib
> +
> +#
> +# The following information is for reference only and not required by t=
he
> build tools.
> +#
> +#  VALID_ARCHITECTURES           =3D IA32
> +#
> +
> +#########################################################
> ##############
> +#########
> +#
> +# Sources Section - list of files that are required for the build to su=
cceed.
> +#
> +#########################################################
> ##############
> +#########
> +
> +[Sources]
> +  PeiPolicyInit.c
> +  PeiPolicyInit.h
> +
> +#########################################################
> ##############
> +#########
> +#
> +# Package Dependency Section - list of Package files that are required =
for
> +#                              this module.
> +#
> +#########################################################
> ##############
> +#########
> +
> +[Packages]
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  KabylakeSiliconPkg/SiPkg.dec
> +  UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses]
> +  SiPolicyLib
> +  DebugLib
> +  PeiServicesLib
> +
> +[Ppis]
> +  gSiDefaultPolicyInitPpiGuid  ## CONSUMES
> +
> +[Pcd]
> +  #
> +  # Below PCD may not be consumed by this library but still adding them
> +here
> +  # to make sure all of them can be built into PcdDataBase.
> +  # Those PCD will be consumed by FSP in dispatch mode as DynamicEx typ=
e.
> +  #
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
> +  gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
> +  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate
> +
> +[Depex]
> +  gSiDefaultPolicyInitPpiGuid
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSi=
liconPol
> icyInitLib.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPr=
eMem
> SiliconPolicyInitLib.inf
> similarity index 83%
> rename from
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSili=
conPolic
> yInitLib.inf
> rename to
> Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreM=
emSili
> conPolicyInitLib.inf
> index 7982a5d87f..782e04a476 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSi=
liconPol
> icyInitLib.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/P
> +++ eiPreMemSiliconPolicyInitLib.inf
> @@ -1,7 +1,7 @@
>  ### @file
>  # Library functions for Policy Initialization Library.
>  #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -14,7 +14,7 @@
> ##########################################################
> ######################
>  [Defines]
>    INF_VERSION                    =3D 0x00010005
> -  BASE_NAME                      =3D PeiSiliconPolicyInitLib
> +  BASE_NAME                      =3D PeiPreMemSiliconPolicyInitLib
>    FILE_GUID                      =3D 80920B16-7778-4793-878E-4555F68BDC=
69
>    MODULE_TYPE                    =3D BASE
>    VERSION_STRING                 =3D 1.0
> @@ -34,7 +34,6 @@
>=20
>  [Sources]
>    PeiPolicyInitPreMem.c
> -  PeiPolicyInit.c
>    PeiPolicyInit.h
>=20
>=20
> ##########################################################
> ######################
> @@ -53,3 +52,9 @@
>    SiPolicyLib
>    DebugLib
>    PeiServicesLib
> +
> +[Ppis]
> +  gSiPreMemDefaultPolicyInitPpiGuid  ## CONSUMES
> +
> +[Depex]
> +  gSiPreMemDefaultPolicyInitPpiGuid
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFsp.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFsp.inf
> index 9ffb84fa1e..c11680656d 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFsp.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs
> +++ p/PeiSiliconPolicyInitLibFsp.inf
> @@ -1,7 +1,7 @@
>  ### @file
>  # Library functions for Fsp Policy Initialization Library.
>  #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -72,6 +72,7 @@
>    MemoryAllocationLib
>    DebugPrintErrorLevelLib
>    FspWrapperApiLib
> +  SiPolicyLib
>=20
>  [Pcd]
>    gSiPkgTokenSpaceGuid.PcdTsegSize                    ## CONSUMES
> @@ -84,7 +85,7 @@
>    gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress    ## CONSUMES
>    gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ##
> CONSUMES
>    gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress    ## CONSUMES
> -
> +
>  [Ppis]
>    gSiPolicyPpiGuid                              ## CONSUMES
>    gSiPreMemPolicyPpiGuid                        ## CONSUMES
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFspAml.inf
> b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFspAml.inf
> index aebd3583bc..1ace9aeb52 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe=
iSilico
> nPolicyInitLibFspAml.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFs
> +++ p/PeiSiliconPolicyInitLibFspAml.inf
> @@ -72,6 +72,7 @@
>    MemoryAllocationLib
>    DebugPrintErrorLevelLib
>    FspWrapperApiLib
> +  SiPolicyLib
>=20
>  [Pcd]
>    gSiPkgTokenSpaceGuid.PcdTsegSize                    ## CONSUMES
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> index a613079dd4..e9d3e5f918 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
> @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid =3D {0xa030d115,
> 0x54dd, 0x447b, { 0x90, 0x64, 0x  ##  gSiPolicyPpiGuid  =3D  {0xaebffa01=
, 0x7edc,
> 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}
> gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x9=
7,
> 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
> +gSiPolicyReadyPpiGuid       =3D {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xe=
e, 0xa5,
> 0x82, 0x7c, 0xe3, 0x17, 0x79}}
> +gSiPreMemPolicyReadyPpiGuid =3D {0x85270bef, 0x6984, 0x4375, {0xa6, 0xe=
a,
> +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGuid
> +=3D  {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63,
> +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid =3D {0xf69abf86, 0x4048, 0x44e=
f,
> +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
>  ##
>  ## SystemAgent
>  ##
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graph=
i
> csPeiConfig.h
> b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graph=
i
> csPeiConfig.h
> index 4063f800e8..b835155c68 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graph=
i
> csPeiConfig.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/G
> +++ raphicsPeiConfig.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Policy definition for Internal Graphics Config Block (PostMem)
>=20
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
>  SPDX-License-Identifier: BSD-2-Clause-Patent
>=20
>  **/
> @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent  **/
> typedef struct {
>    CONFIG_BLOCK_HEADER   Header;                   ///< Offset 0-27 Conf=
ig Block
> Header
> +  UINT32                RenderStandby     : 1;    ///< Offset 28:0 :<b>=
(Test)</b> This
> field is used to enable or disable RC6 (Render Standby): 0=3DFALSE,
> <b>1=3DTRUE</b>
> +  UINT32                PmSupport         : 1;    ///< Offset 28:1 :<b>=
(Test)</b> IGD
> PM Support TRUE/FALSE: 0=3DFALSE, <b>1=3DTRUE</b>
> +  UINT32                PavpEnable        : 1;    ///< Offset 28:2 :IGD=
 PAVP
> TRUE/FALSE: 0=3DFALSE, <b>1=3DTRUE</b>
> +  /**
> +    Offset 28:3
> +    CdClock Frequency select\n
> +    0   =3D 337.5 Mhz, 1 =3D 450 Mhz,\n
> +    2   =3D 540 Mhz,<b> 3 =3D 675 Mhz</b>,\n
> +  **/
> +  UINT32                CdClock            : 3;
>    UINT32                PeiGraphicsPeimInit: 1;   ///< Offset 28:6 :Thi=
s policy is used
> to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
> -  UINT32                RsvdBits0          : 31;  ///< Offser 28:16 :Re=
served for future
> use
> +  UINT32                CdynmaxClampEnable : 1;   ///< Offset 28:7 : Th=
is policy is
> used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>,
> 0- Disable
> +  UINT32                GtFreqMax          : 8;   ///< Offset 28:8 : <b=
>(Test)</b> Max
> GT frequency limited by user in multiples of 50MHz: Default value which
> indicates normal frequency is <b>0xFF</b>
> +  UINT32                RsvdBits0          : 16;  ///< Offser 28:16 :Re=
served for future
> use
>    VOID*                 LogoPtr;                  ///< Offset 32 Addres=
s of Logo to be
> displayed in PEI
>    UINT32                LogoSize;                 ///< Offset 36 Logo S=
ize
>    VOID*                 GraphicsConfigPtr;        ///< Offset 40 Addres=
s of the
> Graphics Configuration Table
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pe=
iS
> aPolicyLib.inf
> b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pe=
iS
> aPolicyLib.inf
> index 8fae4cee61..c7454bd4a5 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pe=
iS
> aPolicyLib.inf
> +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi
> +++ b/PeiSaPolicyLib.inf
> @@ -1,7 +1,7 @@
>  ## @file
>  # Component description file for the PeiSaPolicy library.
>  #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  # @@ -28,6 +28,7 @@
> CpuMailboxLib  SiConfigBlockLib  RngLib  SmbusLib
> +PchCycleDecodingLib
>=20
>  [Packages]
>  MdePkg/MdePkg.dec
> --
> 2.13.3.windows.1
>=20
>=20
>=20