From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Mon, 15 Jul 2019 19:12:49 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jul 2019 19:12:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,496,1557212400"; d="scan'208";a="161276831" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga008.jf.intel.com with ESMTP; 15 Jul 2019 19:12:48 -0700 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 15 Jul 2019 19:12:48 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 15 Jul 2019 19:12:48 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.110]) by shsmsx102.ccr.corp.intel.com ([169.254.2.3]) with mapi id 14.03.0439.000; Tue, 16 Jul 2019 10:12:46 +0800 From: "Ni, Ray" To: "Zeng, Star" CC: "devel@edk2.groups.io" Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin code Thread-Topic: [edk2-devel] [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin code Thread-Index: AQHVOJpno3y2P1TtoU+5PkH6ea8IjKbMf9IAgAAGqYA= Date: Tue, 16 Jul 2019 02:12:46 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C2303EC@SHSMSX104.ccr.corp.intel.com> References: <15B0A143AE80C990.1579@groups.io> <0C09AFA07DD0434D9E2A0C6AEB048310403662D5@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB048310403662D5@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni =20 > -----Original Message----- > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of > Zeng, Star > Sent: Friday, July 12, 2019 6:13 PM > To: devel@edk2.groups.io > Cc: Zeng, Star ; Laszlo Ersek ; > Dong, Eric ; Ni, Ray ; Kumar, > Chandana C ; Li, Kevin Y > > Subject: [edk2-devel] [PATCH] UefiCpuPkg CpuCommonFeaturesLib: > Enhance Ppin code >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1961 > Enhance Ppin code to enable and unlock for TRUE State, and disable and l= ock > for FALSE State. > Note: enable and lock could not be set both. >=20 > Cc: Laszlo Ersek > Cc: Eric Dong > Cc: Ray Ni > Cc: Chandana Kumar > Cc: Kevin Li > Signed-off-by: Star Zeng > --- > .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +++++ > .../CpuCommonFeaturesLib.c | 2 +- > .../Library/CpuCommonFeaturesLib/Ppin.c | 65 +++++++++++++++---- > 3 files changed, 70 insertions(+), 12 deletions(-) >=20 > diff --git > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > index 9e784e916a85..8406c6c1619f 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > @@ -863,6 +863,21 @@ FeatureControlGetConfigData ( > IN UINTN NumberOfProcessors > ); >=20 > +/** > + Prepares for the data used by CPU feature detection and initializatio= n. > + > + @param[in] NumberOfProcessors The number of CPUs in the platform. > + > + @return Pointer to a buffer of CPU related configuration data. > + > + @note This service could be called by BSP only. > +**/ > +VOID * > +EFIAPI > +PpinGetConfigData ( > + IN UINTN NumberOfProcessors > + ); > + > /** > Detects if Protected Processor Inventory Number feature supported on > current > processor. > diff --git > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > index 7cc692efb649..fd43b8d66290 100644 > --- > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > +++ > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > @@ -203,7 +203,7 @@ CpuCommonFeaturesLibConstructor ( > if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { > Status =3D RegisterCpuFeature ( > "PPIN", > - NULL, > + PpinGetConfigData, > PpinSupport, > PpinInitialize, > CPU_FEATURE_PPIN, > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > index e8a4de8dcf60..8067cf44d015 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > @@ -8,6 +8,28 @@ >=20 > #include "CpuCommonFeatures.h" >=20 > +/** > + Prepares for the data used by CPU feature detection and initializatio= n. > + > + @param[in] NumberOfProcessors The number of CPUs in the platform. > + > + @return Pointer to a buffer of CPU related configuration data. > + > + @note This service could be called by BSP only. > +**/ > +VOID * > +EFIAPI > +PpinGetConfigData ( > + IN UINTN NumberOfProcessors > + ) > +{ > + VOID *ConfigData; > + > + ConfigData =3D AllocateZeroPool (sizeof > +(MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors); > + ASSERT (ConfigData !=3D NULL); > + return ConfigData; > +} > + > /** > Detects if Protected Processor Inventory Number feature supported on > current > processor. > @@ -34,6 +56,7 @@ PpinSupport ( > ) > { > MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; > + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; >=20 > if ((CpuInfo->DisplayFamily =3D=3D 0x06) && > ((CpuInfo->DisplayModel =3D=3D 0x3E) || // Xeon E5 V2 > @@ -47,7 +70,12 @@ PpinSupport ( > // Check whether platform support this feature. > // > PlatformInfo.Uint64 =3D AsmReadMsr64 > (MSR_IVY_BRIDGE_PLATFORM_INFO_1); > - return (PlatformInfo.Bits.PPIN_CAP !=3D 0); > + if (PlatformInfo.Bits.PPIN_CAP !=3D 0) { > + MsrPpinCtrl =3D (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; > + ASSERT (MsrPpinCtrl !=3D NULL); > + MsrPpinCtrl[ProcessorNumber].Uint64 =3D AsmReadMsr64 > (MSR_IVY_BRIDGE_PPIN_CTL); > + return TRUE; > + } > } >=20 > return FALSE; > @@ -73,6 +101,7 @@ PpinSupport ( > @retval RETURN_DEVICE_ERROR Device can't change state because it has > been > locked. >=20 > + @note This service could be called by BSP only. > **/ > RETURN_STATUS > EFIAPI > @@ -83,16 +112,18 @@ PpinInitialize ( > IN BOOLEAN State > ) > { > - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl; > + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; > + > + MsrPpinCtrl =3D (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; > + ASSERT (MsrPpinCtrl !=3D NULL); >=20 > // > - // Check whether device already lock this register. > - // If already locked, just base on the request state and > + // Check whether processor already lock this register. > + // If already locked, just based on the request state and > // the current state to return the status. > // > - MsrPpinCtrl.Uint64 =3D AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); > - if (MsrPpinCtrl.Bits.LockOut !=3D 0) { > - return MsrPpinCtrl.Bits.Enable_PPIN =3D=3D State ? RETURN_SUCCESS : > RETURN_DEVICE_ERROR; > + if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut !=3D 0) { > + return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D=3D State ? > + RETURN_SUCCESS : RETURN_DEVICE_ERROR; > } >=20 > // > @@ -106,13 +137,25 @@ PpinInitialize ( > return RETURN_SUCCESS; > } >=20 > - CPU_REGISTER_TABLE_WRITE_FIELD ( > + if (State) { > + // > + // Enable and Unlock. > + // > + MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D 1; > + MsrPpinCtrl[ProcessorNumber].Bits.LockOut =3D 0; } else { > + // > + // Disable and Lock. > + // > + MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D 0; > + MsrPpinCtrl[ProcessorNumber].Bits.LockOut =3D 1; } > + > + CPU_REGISTER_TABLE_WRITE64 ( > ProcessorNumber, > Msr, > MSR_IVY_BRIDGE_PPIN_CTL, > - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER, > - Bits.Enable_PPIN, > - (State) ? 1 : 0 > + MsrPpinCtrl[ProcessorNumber].Uint64 > ); >=20 > return RETURN_SUCCESS; > -- > 2.21.0.windows.1 >=20 >=20 >=20