From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.1477.1571279034362766457 for ; Wed, 16 Oct 2019 19:23:54 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Oct 2019 19:23:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,306,1566889200"; d="scan'208";a="195772500" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga007.fm.intel.com with ESMTP; 16 Oct 2019 19:23:53 -0700 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 16 Oct 2019 19:23:52 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 16 Oct 2019 19:23:52 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.166]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.225]) with mapi id 14.03.0439.000; Thu, 17 Oct 2019 10:23:47 +0800 From: "Ni, Ray" To: "Wang, Iwen Evelyn" , "devel@edk2.groups.io" CC: "Huang, Jenny" , "Shih, More" , "Chaganty, Rangasai V" , "Yao, Jiewen" Subject: Re: [PATCH] IntelSiliconPkg-Vtd: Code Optimization Thread-Topic: [PATCH] IntelSiliconPkg-Vtd: Code Optimization Thread-Index: AQHVhHXHYglVud7owEW6ULxhYnoZhadeGlXw Date: Thu, 17 Oct 2019 02:23:46 +0000 Deferred-Delivery: Thu, 17 Oct 2019 02:22:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3257CF@SHSMSX104.ccr.corp.intel.com> References: <20191016230153.2392-1-iwen.evelyn.wang@intel.com> In-Reply-To: <20191016230153.2392-1-iwen.evelyn.wang@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Wang, Iwen Evelyn > Sent: Thursday, October 17, 2019 7:02 AM > To: devel@edk2.groups.io > Cc: Huang, Jenny ; Shih, More > ; Ni, Ray ; Chaganty, Rangasai V > ; Yao, Jiewen > Subject: [PATCH] IntelSiliconPkg-Vtd: Code Optimization >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 >=20 > 1) DisableDMAr Function Code Optimization Optimize the flow to follow the > VT-d spec requirements. >=20 > 2) Renamed InitDmar() to InitGlobalVtd() The oringal function name is > misleading >=20 > Signed-off-by: Evelyn Wang > Cc: Jenny Huang > Cc: More Shih > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Jiewen Yao > --- > Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > | 30 +++++++++++++++++++++++++++--- > Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > | 29 ++++++++++++++++++++++++++--- >=20 > Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platfo= r > mVTdInfoSamplePei.c | 9 +++++---- > 3 files changed, 58 insertions(+), 10 deletions(-) >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg= .c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > index 22bf821d2b..699639ba88 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -309,6 +309,8 @@ DisableDmar ( > UINTN Index; > UINTN SubIndex; > UINT32 Reg32; > + UINT32 Status; > + UINT32 Command; >=20 > for (Index =3D 0; Index < mVtdUnitNumber; Index++) { > DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", > Index)); @@ -319,9 +321,31 @@ DisableDmar ( > FlushWriteBuffer (Index); >=20 > // > - // Disable VTd > + // Disable Dmar > // > - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > R_GCMD_REG, B_GMCD_REG_SRTP); > + // > + // Set TE (Translation Enable: BIT31) of Global command register to = zero > + // > + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress > + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status & ~B_GMCD_REG_TE); > + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > + R_GCMD_REG, Command); > + > + // > + // Poll on TE Status bit of Global status register to become zero > + // > + do { > + Reg32 =3D MmioRead32 > (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG); > + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); > + > + // > + // Set SRTP (Set Root Table Pointer: BIT30) of Global command regist= er in > order to update the root table pointerDisable VTd > + // > + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress > + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status | B_GMCD_REG_SRTP); > + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + > + R_GCMD_REG, Command); > + > do { > Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddres= s > + R_GSTS_REG); > } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > index 4774a2ae5b..c9669426aa 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -197,6 +197,8 @@ DisableDmar ( > ) > { > UINT32 Reg32; > + UINT32 Status; > + UINT32 Command; >=20 > DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", > VtdUnitBaseAddress)); >=20 > @@ -206,9 +208,30 @@ DisableDmar ( > FlushWriteBuffer (VtdUnitBaseAddress); >=20 > // > - // Disable VTd > + // Disable Dmar > // > - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, > B_GMCD_REG_SRTP); > + // > + // Set TE (Translation Enable: BIT31) of Global command register to > + zero // > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status & ~B_GMCD_REG_TE); > + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); > + > + // > + // Poll on TE Status bit of Global status register to become zero > + // > + do { > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); > + > + // > + // Set SRTP (Set Root Table Pointer: BIT30) of Global command > + register in order to update the root table pointerDisable VTd // > + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits > + Command =3D (Status | B_GMCD_REG_SRTP); > + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); > do { > Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); > } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Plat= f > ormVTdInfoSamplePei.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Plat= f > ormVTdInfoSamplePei.c > index 3698c3d3f1..6f6c14f7a9 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Plat= f > ormVTdInfoSamplePei.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei > +++ /PlatformVTdInfoSamplePei.c > @@ -1,7 +1,7 @@ > /** @file > Platform VTd Info Sample PEI driver. >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR > mPlatformVTdNoIgdInfoSampleDesc =3D { >=20 > /** > Initialize VTd register. > + Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set > **/ > VOID > -InitDmar ( > +InitGlobalVtd ( > VOID > ) > { > UINT32 MchBar; >=20 > - DEBUG ((DEBUG_INFO, "InitDmar\n")); > + DEBUG ((DEBUG_INFO, "InitGlobalVtd\n")); >=20 > MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; > PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0); > @@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize ( > DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized)); > if (!SiliconInitialized) { > Status =3D PeiServicesNotifyPpi (&mSiliconInitializedNotifyList); > - InitDmar (); > + InitGlobalVtd (); >=20 > Status =3D PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc); > ASSERT_EFI_ERROR (Status); > -- > 2.16.2.windows.1