From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.2484.1571289046709747160 for ; Wed, 16 Oct 2019 22:10:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Oct 2019 22:10:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,306,1566889200"; d="scan'208";a="186375677" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga007.jf.intel.com with ESMTP; 16 Oct 2019 22:10:19 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 16 Oct 2019 22:10:18 -0700 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 16 Oct 2019 22:10:18 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.166]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.225]) with mapi id 14.03.0439.000; Thu, 17 Oct 2019 13:10:15 +0800 From: "Ni, Ray" To: "Wang, Iwen Evelyn" , "devel@edk2.groups.io" CC: "Huang, Jenny" , "Shih, More" , "Chaganty, Rangasai V" , "Yao, Jiewen" Subject: Re: [v7 v7] IntelSiliconPkg-Vtd: A new PMR interface Thread-Topic: [v7 v7] IntelSiliconPkg-Vtd: A new PMR interface Thread-Index: AQHVhJntfqIp7E/Vf0SK2poBuZePIadeSJXw Date: Thu, 17 Oct 2019 05:10:14 +0000 Deferred-Delivery: Thu, 17 Oct 2019 05:09:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3258DE@SHSMSX104.ccr.corp.intel.com> References: <20191017032101.14764-1-iwen.evelyn.wang@intel.com> In-Reply-To: <20191017032101.14764-1-iwen.evelyn.wang@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Wang, Iwen Evelyn > Sent: Thursday, October 17, 2019 11:21 AM > To: devel@edk2.groups.io > Cc: Huang, Jenny ; Shih, More > ; Ni, Ray ; Chaganty, Rangasai V > ; Yao, Jiewen > Subject: [v7 v7] IntelSiliconPkg-Vtd: A new PMR interface >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 >=20 > 1) IOMMU PMR feature should be generic to support different hardware > architecture. Platforms may request no overlap between PMR regions and > system reserve memory. Create an interface to control PLMR/PHMR regions. > It allows silicon code to adjust PLMR/PHMR region base on the project nee= ds. >=20 > 2) A new GetVtdPmrAlignmentLib for silicon code to get PMR alignment > values. >=20 > Signed-off-by: Evelyn Wang > Cc: Jenny Huang > Cc: More Shih > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Jiewen Yao >=20 > --- > In V2: > 1) Fixed the EFIAPI is missing in library API issue > 2) Logs will be provided to make sure the backwards compatibility > 3) Replaced BIT0 with EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL > 4) Renamed GetVtdPmrAlignmentLib to PeiGetVtdPmrAlignmentLib > 5) Fixed the indent in IntelVTdPmrPei.c > 6) Follow VTd spec to define the data type of the SYSTEM_MEM_INFO_HOB > Applied few changes coordinately >=20 > --- > In V3: > 1) Fixed the EFIAPI is missing in library API issue > 2) Fixed the S3 resume assert >=20 > --- > In V4: > Fixed the missing EFIAPI in .h file and added few more comments >=20 > --- > In V5: > In order to align with the future planning, changed the hob name from > SYSTEM_MEM_INFO_HOB to VTD_PMR_INFO_HOB >=20 > --- > In V6: > 1) Revised comments > 2) Moved VtdPmrInfoHob.h under Guid folder > 3) Separated to few commits >=20 > --- > In V7: > 1) Only the functions declared in library header file should have EFIAPI > 2) Added a few comments to avoid confusion > 3) Fixed a case error > --- > Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c > | 4 ++-- > Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.= c > | 84 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++----------------------- >=20 > Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdP > mrAlignmentLib.c | 164 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++ >=20 > Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.i= n > f | 5 ++++- > Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h > | 29 +++++++++++++++++++++++++++++ > Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h > | 22 ++++++++++++++++++++++ > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 11 > +++++++++-- > Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = | 3 ++- >=20 > Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdP > mrAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++ > 9 files changed, 325 insertions(+), 29 deletions(-) >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c > index 37283f0fab..9103e53922 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP > +++ mr.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -294,7 +294,7 @@ SetDmaProtectedRange ( > UINTN Index; > EFI_STATUS Status; >=20 > - DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] > [0x%lx, 0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, > HighMemoryBase, HighMemoryLength)); > + DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] > + [0x%016lx, 0x%016lx]\n", EngineMask, LowMemoryBase, > LowMemoryLength, > + HighMemoryBase, HighMemoryLength)); >=20 > for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { > if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .c > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .c > index ca099ed71d..ea944aa40c 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP > +++ mrPei.c > @@ -1,6 +1,6 @@ > /** @file >=20 > - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2017 - 2019, Intel Corporation. All rights > + reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -20,7 +20,7 @@ > #include > #include > #include > - > +#include > #include "IntelVTdPmrPei.h" >=20 > EFI_GUID mVTdInfoGuid =3D { > @@ -424,37 +424,79 @@ InitDmaProtection ( > UINTN MemoryAlignment; > UINTN LowBottom; > UINTN LowTop; > - UINTN HighBottom; > + UINT64 HighBottom; > UINT64 HighTop; > DMA_BUFFER_INFO *DmaBufferInfo; > VOID *Hob; > EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; > EDKII_IOMMU_PPI *OldIoMmuPpi; > + VTD_PMR_INFO_HOB *VtdPmrHob; > + VOID *VtdPmrHobPtr; >=20 > + // > + // Initialization > + // > + VtdPmrHob =3D NULL; > Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); > DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); > + VtdPmrHobPtr =3D GetFirstGuidHob (&gVtdPmrInfoDataHobGuid); > + > + /** > + When gVtdPmrInfoDataHobGuid exists, it means: > + 1. Dma buffer is reserved by memory initialize code > + 2. PeiGetVtdPmrAlignmentLib is used to get alignment > + 3. PMR regions are determined by the system memory map > + 4. PMR regions will be conveyed through VTD_PMR_INFO_HOB > + > + When gVtdPmrInfoDataHobGuid dosen't exist, it means: > + 1. IntelVTdPmr driver will calcuate the PMR memory alignment > + 2. Dma buffer is reserved by AllocateAlignedPages() **/ if > + (VtdPmrHobPtr =3D=3D NULL) { > + // > + // Calcuate the PMR memory alignment > + // > + DEBUG ((DEBUG_INFO, "No special requirements for PMR memory\n")); > + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo- > >EngineMask); > + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo- > >EngineMask); > + if (LowMemoryAlignment < HighMemoryAlignment) { > + MemoryAlignment =3D (UINTN)HighMemoryAlignment; > + } else { > + MemoryAlignment =3D LowMemoryAlignment; > + } > + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D > + ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment)); >=20 > - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo- > >DmaBufferSize)); > + // > + // Allocate memory for DMA buffer > + // > + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages > (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); > + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); > + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { > + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); > + return EFI_OUT_OF_RESOURCES; > + } >=20 > - LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo- > >EngineMask); > - HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo- > >EngineMask); > - if (LowMemoryAlignment < HighMemoryAlignment) { > - MemoryAlignment =3D (UINTN)HighMemoryAlignment; > + LowBottom =3D 0; > + LowTop =3D DmaBufferInfo->DmaBufferBase; > + HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo- > >DmaBufferSize; > + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); > } else { > - MemoryAlignment =3D LowMemoryAlignment; > - } > - ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D > ALIGN_VALUE(DmaBufferInfo->DmaBufferSize, MemoryAlignment)); > - DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages > (EFI_SIZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); > - ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); > - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { > - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); > - return EFI_OUT_OF_RESOURCES; > - } >=20 > - DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo- > >DmaBufferBase)); > + // > + // Get the PMR ranges information for the VTd PMR hob > + // > + VtdPmrHob =3D GET_GUID_HOB_DATA (VtdPmrHobPtr); > + DmaBufferInfo->DmaBufferBase =3D VtdPmrHob->ProtectedLowLimit; > + LowBottom =3D VtdPmrHob->ProtectedLowBase; > + LowTop =3D VtdPmrHob->ProtectedLowLimit; > + HighBottom =3D VtdPmrHob->ProtectedHighBase; > + HighTop =3D VtdPmrHob->ProtectedHighLimit; } >=20 > DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase > + DmaBufferInfo->DmaBufferSize; > DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo- > >DmaBufferBase; > + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", > + DmaBufferInfo->DmaBufferSize)); DEBUG ((DEBUG_INFO, " > DmaBufferBase : > + 0x%x\n", DmaBufferInfo->DmaBufferBase)); >=20 > // > // (Re)Install PPI. > @@ -472,10 +514,6 @@ InitDmaProtection ( > } > ASSERT_EFI_ERROR (Status); >=20 > - LowBottom =3D 0; > - LowTop =3D DmaBufferInfo->DmaBufferBase; > - HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo- > >DmaBufferSize; > - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); >=20 > Status =3D SetDmaProtectedRange ( > VTdInfo, > @@ -559,7 +597,7 @@ InitVTdPmrForAll ( > VTD_INFO *VTdInfo; > UINTN LowBottom; > UINTN LowTop; > - UINTN HighBottom; > + UINT64 HighBottom; > UINT64 HighTop; >=20 > Hob =3D GetFirstGuidHob (&mVTdInfoGuid); diff --git > a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVt > dPmrAlignmentLib.c > b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVt > dPmrAlignmentLib.c > new file mode 100644 > index 0000000000..8471cf85ac > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/Pei > +++ GetVtdPmrAlignmentLib.c > @@ -0,0 +1,164 @@ > +/** @file > + Library to get Global VTd PMR alignment information. > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +typedef union { > + struct { > + UINT32 Low; > + UINT32 High; > + } Data32; > + UINT64 Data; > +} UINT64_STRUCT; > + > +/** > + Get protected low memory alignment. > + > + @param HostAddressWidth The host address width. > + @param VtdUnitBaseAddress The base address of the VTd engine. > + > + @return protected low memory alignment. Ex: 0x100000 **/ > +UINT32 > +GetGlobalVTdPlmrAlignment ( > + IN UINT8 HostAddressWidth, > + IN UINTN VtdUnitBaseAddress > + ) > +{ > + UINT32 Data32; > + > + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, > 0xFFFFFFFF); > + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); > + Data32 =3D ~Data32 + 1; > + > + return Data32; > +} > + > +/** > + Get protected high memory alignment. > + > + @param HostAddressWidth The host address width. > + @param VtdUnitBaseAddress The base address of the VTd engine. > + > + @return protected high memory alignment. Ex: 0x100000 **/ > +UINT64_STRUCT GetGlobalVTdPhmrAlignment ( > + IN UINT8 HostAddressWidth, > + IN UINTN VtdUnitBaseAddress > + ) > +{ > + UINT64_STRUCT Data64; > + > + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, > + 0xFFFFFFFFFFFFFFFF); Data64.Data =3D MmioRead64 (VtdUnitBaseAddress + > + R_PMEN_HIGH_BASE_REG); Data64.Data =3D ~Data64.Data + 1; Data64.Data > =3D > + Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1); > + > + return Data64; > +} > + > +/** > + Get Global VT-d Protected Memory alignment. > + @return The maximum protected memory alignment. Ex: 0x100000 **/ > +UINTN EFIAPI GetGlobalVtdPmrAlignment ( > +) > +{ > + UINT32 LowMemoryAlignment; > + UINT64_STRUCT HighMemoryAlignment; > + UINTN MemoryAlignment; > + UINT32 GlobalVTdBaseAddress; > + EFI_STATUS Status; > + UINTN VtdIndex; > + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; > + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader; > + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; > + > + // > + // Initialization > + // > + GlobalVTdBaseAddress =3D 0xFFFFFFFF; > + LowMemoryAlignment =3D 0; > + HighMemoryAlignment.Data =3D 0; > + MemoryAlignment =3D 0; > + Status =3D EFI_UNSUPPORTED; > + VtdIndex =3D 0; > + DmarHeader =3D NULL; > + DrhdHeader =3D NULL; > + AcpiDmarTable =3D NULL; > + > + // > + // Fatch the PEI DMAR ACPU Table that created and installed in > + PlatformVTdInfoSamplePei.c // Status =3D PeiServicesLocatePpi ( > + &gEdkiiVTdInfoPpiGuid, > + 0, > + NULL, > + (VOID **)&AcpiDmarTable > + ); > + if (EFI_ERROR (Status)) { > + > + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid > failed\n")); > + Status =3D EFI_NOT_FOUND; > + MemoryAlignment =3D SIZE_1MB; > + > + } else { > + > + // > + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global > VT-d > + // > + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER > *)((UINTN)(AcpiDmarTable + 1)); > + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable- > >Header.Length) { > + switch (DmarHeader->Type) { > + case EFI_ACPI_DMAR_TYPE_DRHD: > + DrhdHeader =3D (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader; > + if ((DrhdHeader->Flags & > EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) =3D=3D > EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) { > + GlobalVTdBaseAddress =3D (UINT32)DrhdHeader->RegisterBaseAddre= ss; > + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", > GlobalVTdBaseAddress)); > + } > + VtdIndex++; > + > + break; > + > + default: > + break; > + } > + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER > *)((UINTN)DmarHeader + DmarHeader->Length); > + } > + > + if (GlobalVTdBaseAddress =3D=3D 0xFFFFFFFF) { > + > + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to > your Global VT-d\n")); > + MemoryAlignment =3D SIZE_1MB; > + > + } else { > + // > + // Get the alignment information from VT-d register > + // > + LowMemoryAlignment =3D GetGlobalVTdPlmrAlignment (AcpiDmarTable- > >HostAddressWidth, GlobalVTdBaseAddress); > + HighMemoryAlignment =3D GetGlobalVTdPhmrAlignment (AcpiDmarTable- > >HostAddressWidth, GlobalVTdBaseAddress); > + if (LowMemoryAlignment < HighMemoryAlignment.Data) { > + MemoryAlignment =3D (UINTN)HighMemoryAlignment.Data; > + } else { > + MemoryAlignment =3D LowMemoryAlignment; > + } > + } > + } > + > + return MemoryAlignment; > +} > diff --git > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .inf > b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .inf > index 39b914cd00..3eb2b510ca 100644 > --- > a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei > .inf > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdP > +++ mrPei.inf > @@ -4,7 +4,7 @@ > # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI # an= d > provide DMA protection in PEI. > # > -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -40,6 +40,9 @@ > IoLib > CacheMaintenanceLib >=20 > +[Guids] > + gVtdPmrInfoDataHobGuid ## CONSUMES > + > [Ppis] > gEdkiiIoMmuPpiGuid ## PRODUCES > gEdkiiVTdInfoPpiGuid ## CONSUMES > diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h > b/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h > new file mode 100644 > index 0000000000..d08b9818e3 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/VtdPmrInfoHob.h > @@ -0,0 +1,29 @@ > +/** @file > + The definition for VTD PMR Regions Information Hob. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > + > +#ifndef _VTD_PMR_INFO_HOB_H_ > +#define _VTD_PMR_INFO_HOB_H_ > + > +/// > +/// This interface is to report the PMR regions information /// PMR > +regions means PLMR/PHMR base and limit /// When > gVtdPmrInfoDataHobGuid > +exists, it means: > +/// 1. Dma buffer is reserved by memory initialize code /// 2. > +PeiGetVtdPmrAlignmentLib is used to get alignment /// 3. PMR regions > +are determined by the system memory map /// 4. PMR regions will be > +conveyed through VTD_PMR_INFO_HOB /// typedef struct { > + UINT32 ProtectedLowBase; //PLMR Base > + UINT32 ProtectedLowLimit; //PLMR Limit > + UINT64 ProtectedHighBase; //PHMR Base > + UINT64 ProtectedHighLimit; //PHMR Limit > +} VTD_PMR_INFO_HOB; > + > +#endif // _VTD_PMR_INFO_HOB_H_ > + > diff --git > a/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.= h > b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.= h > new file mode 100644 > index 0000000000..c6918d34d5 > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmen > +++ tLib.h > @@ -0,0 +1,22 @@ > +/** @file > + Get Global VTd PMR alignment information library. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__ > +#define __GET_VTD_PMR_ALIGN_LIB_H__ > +#include > + > +/** > + Get Global VT-d Protected Memory alignment. > + @return The maximum protected memory alignment. > +**/ > + > +UINTN > +EFIAPI > +GetGlobalVtdPmrAlignment ( > +); > + > +#endif // __GET_VTD_PMR_ALIGN_LIB_H__ > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > index fe5bfa0dc6..5e8082e113 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec > @@ -3,7 +3,7 @@ > # > # This package provides common open source Intel silicon modules. > # > -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2016 - 2019, Intel Corporation. All rights > +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -18,10 +18,14 @= @ > Include >=20 > [LibraryClasses.IA32, LibraryClasses.X64] > - ## @libraryclass Provides services to access Microcode region on flas= h > device. > + ## @libraryclass Provides services to access Microcode region on flash > device. > # > MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h >=20 > + ## @libraryclass Provides services to access VTd PMR information # > + PeiGetVtdPmrAlignmentLib|Include/Library/PeiGetVtdPmrAlignmentLib.h > + > [Guids] > ## GUID for Package token space > # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735} > @@ -35,6 +39,9 @@ > ## Include/Guid/MicrocodeFmp.h > gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, { = 0x9d, > 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } >=20 > + ## HOB GUID to get memory information after MRC is done. The hob data > + will be used to set the PMR ranges gVtdPmrInfoDataHobGuid =3D > + {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0xb5, 0x02, 0x38, 0x5e, > + 0xe7, 0xe7 } } > + > [Ppis] > gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0= x67, > 0xaf, 0x2b, 0x25, 0x68, 0x4a } } >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc > b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc > index 58b5b656ef..352d1e2b6d 100644 > --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc > +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc > @@ -1,7 +1,7 @@ > ## @file > # This package provides common open source Intel silicon modules. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -34,6 +34,7 @@ >=20 > SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.= in > f >=20 > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCac > heMaintenanceLib.inf >=20 > MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod > eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf > + > + > PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignment > + Lib/PeiGetVtdPmrAlignmentLib.inf >=20 > [LibraryClasses.common.PEIM] > PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf > diff --git > a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVt > dPmrAlignmentLib.inf > b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVt > dPmrAlignmentLib.inf > new file mode 100644 > index 0000000000..ebb2cc2a7f > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/Pei > +++ GetVtdPmrAlignmentLib.inf > @@ -0,0 +1,32 @@ > +## @file > +# Component INF file for the GetVtdPmrAlignment library. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > + > +[Defines] > +INF_VERSION =3D 0x00010017 > +BASE_NAME =3D PeiGetVtdPmrAlignmentLib > +FILE_GUID =3D 0332BE93-0547-4D87-A7FA-0D9D76C53187 > +MODULE_TYPE =3D BASE > +LIBRARY_CLASS =3D PeiGetVtdPmrAlignmentLib > + > +[Packages] > +MdePkg/MdePkg.dec > +IntelSiliconPkg/IntelSiliconPkg.dec > + > +[Sources] > +PeiGetVtdPmrAlignmentLib.c > + > +[LibraryClasses] > +DebugLib > +BaseMemoryLib > +MemoryAllocationLib > +BaseLib > +PeiServicesLib > + > +[Ppis] > +gEdkiiVTdInfoPpiGuid ## CONSUMES > -- > 2.16.2.windows.1