From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.197.1573102010537698680 for ; Wed, 06 Nov 2019 20:46:50 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2019 20:46:50 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,276,1569308400"; d="scan'208";a="353690447" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga004.jf.intel.com with ESMTP; 06 Nov 2019 20:46:50 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 20:46:49 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 6 Nov 2019 20:46:49 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.127]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.248]) with mapi id 14.03.0439.000; Thu, 7 Nov 2019 12:46:47 +0800 From: "Ni, Ray" To: "Yao, Jiewen" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Lou, Yun" Subject: Re: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVj+cqqpetw0q8vUm1qNVz1UGmrKd/LCrA Date: Thu, 7 Nov 2019 04:46:46 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C352D67@SHSMSX104.ccr.corp.intel.com> References: <20191031123127.10900-1-jiewen.yao@intel.com> <20191031123127.10900-2-jiewen.yao@intel.com> In-Reply-To: <20191031123127.10900-2-jiewen.yao@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jiewen, You could use "UINT8 Digest[0];" in structure INTEL_PCI_DIGEST_CAPABILITY_S= TRUCTURE. Same comments as what Sai raised, better to have the referenced spec in the= file header. Thanks, Ray > -----Original Message----- > From: Yao, Jiewen > Sent: Thursday, October 31, 2019 8:31 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Lou, Yun > Subject: [PATCH V2 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity > definition. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Yun Lou > Signed-off-by: Jiewen Yao > --- > Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.= h | > 66 ++++++++++++++++++++ > 1 file changed, 66 insertions(+) >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > new file mode 100644 > index 0000000000..a8c5483165 > --- /dev/null > +++ > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > @@ -0,0 +1,66 @@ > +/** @file > + Intel PCI security data structure > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __INTEL_PCI_SECURITY_H__ > +#define __INTEL_PCI_SECURITY_H__ > + > +#pragma pack(1) > + > +typedef struct { > + UINT16 CapId; // 0x23: DVSEC > + UINT16 CapVersion:4; // 1 > + UINT16 NextOffset:12; > + UINT16 DvSecVendorId; // 0x8086 > + UINT16 DvSecRevision:4; // 1 > + UINT16 DvSecLength:12; > + UINT16 DvSecId; // 0x3E: Measure > +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; > + > +#define INTEL_PCI_CAPID_DVSEC 0x23 > +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 > +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E > + > +typedef union { > + struct { > + UINT8 DigestModified:1; // RW1C > + UINT8 Reserved0:7; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_MODIFIED; > + > +#define INTEL_PCI_DIGEST_MODIFIED BIT0 > + > +typedef union { > + struct { > + UINT8 Digest0Valid:1; // RO > + UINT8 Digest0Locked:1; // RO > + UINT8 Digest1Valid:1; // RO > + UINT8 Digest1Locked:1; // RO > + UINT8 Reserved1:4; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_VALID; > + > +#define INTEL_PCI_DIGEST_0_VALID BIT0 > +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 > +#define INTEL_PCI_DIGEST_1_VALID BIT2 > +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 > + > +typedef struct { > + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C > + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO > + UINT16 TcgAlgId; // RO > + UINT8 FirmwareID; // RO > + UINT8 Reserved; > +//UINT8 Digest[]; > +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; > + > +#pragma pack() > + > +#endif > + > -- > 2.19.2.windows.1