From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.6459.1573193519162390942 for ; Thu, 07 Nov 2019 22:11:59 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 22:11:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,280,1569308400"; d="scan'208";a="214836371" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga002.jf.intel.com with ESMTP; 07 Nov 2019 22:11:58 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 22:11:58 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 22:11:57 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.127]) by shsmsx102.ccr.corp.intel.com ([169.254.2.108]) with mapi id 14.03.0439.000; Fri, 8 Nov 2019 14:11:56 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 00/12] New PCI features - MPS, MRRS, RO, NS, CTO Thread-Index: AQHVkULbej08Z3wkQ0uCOUT+82//4KeAsYpAgAAgg4A= Date: Fri, 8 Nov 2019 06:11:56 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C354E8F@SHSMSX104.ccr.corp.intel.com> References: <15D34310CBE1F8C3.20918@groups.io> <95C5C2B113DE604FB208120C742E982457909893@BGSMSX101.gar.corp.intel.com> In-Reply-To: <95C5C2B113DE604FB208120C742E982457909893@BGSMSX101.gar.corp.intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ashraf, For such a big change, can you please create a branch in github in your per= sonal repo? It helps a lot for code review. Or can you please reply the mail with all patches attached? Groups.io suppo= rts attachments. Thanks, Ray > -----Original Message----- > From: Javeed, Ashraf > Sent: Friday, November 8, 2019 12:10 PM > To: devel@edk2.groups.io; Javeed, Ashraf > Cc: Wang, Jian J ; Wu, Hao A ; > Ni, Ray > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 > 00/12] New PCI features - MPS, MRRS, RO, NS, CTO >=20 > Hi Jian, Hao, and Ray; > Kindly review my patch set from 1 to 12 to enhance the PCI Bus driver to > support the new PCI features.. >=20 > Thanks > Ashraf >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of > Javeed, > > Ashraf > > Sent: Saturday, November 2, 2019 11:30 AM > > To: devel@edk2.groups.io > > Cc: Wang, Jian J ; Wu, Hao A > > ; Ni, Ray > > Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH V2 > 00/12] > > New PCI features - MPS, MRRS, RO, NS, CTO > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > > > > The EDK2 Kernel PciBusDxe driver is enhanced to enable the > > configuration of PCI features like > > (1) Max_Payload_Size > > (2) Max_Read_Req_Size > > (3) Relax Ordering > > (4) No-Snoop > > (5) Completion Timeout > > > > Max_Payload_Size:- The PCI Device Control register provides this > > feature register field which controls the maximum data packet (TLP) > > size that a PCI device should maintain as a requester. The PCI Bus > > driver is required to maintain a highest common value supported by all > > the PCI devices in a PCIe hierarchy, especially in case of isochronous > applications. > > > > Max_Read_Req_Size:- The PCI Device Control register provides this > > feature register field which controls the maximum memory read request > > size that a PCI device should maintain as a requester. The PCI Bus > > driver is required to maintain a common value, same as > > Max_Payload_Size, in case of isochronous applications only; or else, > > it should maintain the user requested value uniformly in a PCIe hierarc= hy > (PCI root port and its downstream devices). > > > > Relax Ordering:- The PCI Device Control register has the enabling of > > Relax Ordering functionality register field (bit 4). If this bit is > > Set, the PCI Function is permitted to set the Relaxed Ordering bit in > > the Attributes field of transactions it initiates that do not require > > strong write ordering (see PCI Base Specification 4, Section 2.2.6.4 > > and Sect- ion 2.4). Any supporting PCI function is expected have this > > bit enabled as per its hardware default; the code enhancement is to > > enable / disable as per the PCI device policy provided by the platform > > firmware. If no device policy override is provided than it shall be ign= ored by > the PCI Bus driver for that PCI function. > > > > No-Snoop:- The PCI Device Control register has the enabling of > > No-Snoop functionality register field (bit 11). If this bit is Set, > > the PCI Function is permitted to Set the No Snoop bit in the Requester > > Attributes of transactions it initiates that do not require hardware > > enforced cache coherency (see PCI Base Specification 4, Section > > 2.2.6.5). Any supporting PCI function is expected have this bit > > enabled as per its hardware default; the code enhancement is to enable > > / disable as per the PCI device policy provided by the platform > > firmware. If no device policy override is provided than it shall be ign= ored by > the PCI Bus driver for that PCI function. > > > > Completion Timeout:- The PCI Device Control 2 register provides two > > register fields based on its Device Capability 2 register; the CTO > > Ranges (bits [3:0]) and the disabling of CTO detection mechanism (bit > > 4). The software is permitted to change the CTO ranges and > > enable/disable the CTO detection mechanism any time. The code > > enhancement here is to override these register fields as per the > > platform device policy. If no device policy override is provided than i= t shall > be ignored by the PCI Bus driver for that PCI function. > > > > The PCI Base Specification 4 Revision 1 contains detailed information > > about these features. The EDK2 PCI Bus driver needs to enable the > > configuration of these features as per the PCI Base specification. > > > > The EDK2 PCI Bus driver also needs to take the PCI device-specific > > platform policy into the consideration while programming these > > features; thus the code changes to support these, is explicitly > > dependent on the new PCI Platform Protocol interface definition > > defined in the below > > record:- > > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > > > > > > Signed-off-by: Ashraf Javeed > > Cc: Jian J Wang > > Cc: Hao A Wu > > Cc: Ray Ni > > --- > > > > V2: Fixed message format and added feature change reference links > > --- > > > > Ashraf Javeed (12): > > MdeModulePkg/PciBusDxe:New PCI features separation with PCD > > PciBusDxe: Reorganize the PCI Platform Protocol usage code > > PciBusDxe: Separation of the PCI device registration and start > > PciBusDxe: Inclusion of new PCI Platform Protocol 2 > > PciBusDxe: Setup sub-phases for PCI feature enumeration > > PciBusDxe: Integration of setup for PCI feature enumeration > > PciBusDxe: Record the PCI-Express Capability Structure > > PciBusDxe: New PCI feature Max_Payload_Size > > PciBusDxe: New PCI feature Max_Read_Req_Size > > PciBusDxe: New PCI feature Relax Ordering > > PciBusDxe: New PCI feature No-Snoop > > PciBusDxe: New PCI feature Completion Timeout > > > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 +--------= -- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 20 ++++++++-= - > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 9 ++++- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 233 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > +++++-------------------------------------- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 > > ++++++++++++++++------------------------------------------------- > > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 > > ++++++++++------ > > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 2030 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > +++++++++++++++++++++++++++ > > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 223 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > ++++++++++++++++++++++++++++++++++++++ > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 749 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > +++++++++++++++++++++ > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 191 > > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++ > > ++++++++++++++++++++++++ > > MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +------ > > MdeModulePkg/MdeModulePkg.dec | 22 +++++++++= ++ > > 12 files changed, 3450 insertions(+), 238 deletions(-) create mode > > 100644 MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > > create mode 100644 > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > create mode 100644 > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > create mode 100644 > > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > -- > > 2.21.0.windows.1 > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > Groups.io Links: You receive all messages sent to this group. > > > > View/Reply Online (#49883): > > https://edk2.groups.io/g/devel/message/49883 > > Mute This Topic: https://groups.io/mt/40632595/1835458 > > Group Owner: devel+owner@edk2.groups.io > > Unsubscribe: https://edk2.groups.io/g/devel/unsub > > [ashraf.javeed@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D