From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.6355.1573196310166769924 for ; Thu, 07 Nov 2019 22:58:30 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 22:58:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,280,1569308400"; d="scan'208";a="286251555" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 07 Nov 2019 22:58:29 -0800 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 22:58:28 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 22:58:28 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.127]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.2]) with mapi id 14.03.0439.000; Fri, 8 Nov 2019 14:58:27 +0800 From: "Ni, Ray" To: "Yao, Jiewen" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Lou, Yun" Subject: Re: [PATCH V3 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Topic: [PATCH V3 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity definition. Thread-Index: AQHVlXCrlTEsf9PeD0eTfQYUrbhxE6eA2IAQ Date: Fri, 8 Nov 2019 06:58:27 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C354F65@SHSMSX104.ccr.corp.intel.com> References: <20191107133831.22412-1-jiewen.yao@intel.com> <20191107133831.22412-2-jiewen.yao@intel.com> In-Reply-To: <20191107133831.22412-2-jiewen.yao@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Yao, Jiewen > Sent: Thursday, November 7, 2019 9:38 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Lou, Yun > Subject: [PATCH V3 1/6] IntelSiliconPkg/Include: Add Intel PciSecurity > definition. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2303 >=20 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Yun Lou > Signed-off-by: Jiewen Yao > --- > .../IndustryStandard/IntelPciSecurity.h | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 > Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity.h >=20 > diff --git > a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSecurity= .h > new file mode 100644 > index 0000000000..f2bdb7ee2d > --- /dev/null > +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IntelPciSec > +++ urity.h > @@ -0,0 +1,92 @@ > +/** @file > + Intel PCI security data structure definition from > + PCIe* Device Security Enhancements Specification. > + > + > + https://www.intel.com/content/www/us/en/io/pci-express/pcie-device- > sec > + urity-enhancements-spec.html > + > + NOTE: The data structure is not fully match the current > + specification, because it is aligned with the real hardware > + implementation with minor adjustment on > + INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE, > INTEL_PCI_DIGEST_DATA_MODIFIED and INTEL_PCI_DIGEST_DATA_VALID. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef __INTEL_PCI_SECURITY_H__ > +#define __INTEL_PCI_SECURITY_H__ > + > +#pragma pack(1) > + > +/// > +/// The PCIE capability structure header for Intel PCI DVSEC extension. > +/// > +typedef struct { > + UINT16 CapId; // 0x23: DVSEC > + UINT16 CapVersion:4; // 1 > + UINT16 NextOffset:12; > + UINT16 DvSecVendorId; // 0x8086 > + UINT16 DvSecRevision:4; // 1 > + UINT16 DvSecLength:12; > + UINT16 DvSecId; // 0x3E: Measure > +} INTEL_PCI_DIGEST_CAPABILITY_HEADER; > + > +#define INTEL_PCI_CAPID_DVSEC 0x23 > +#define INTEL_PCI_DVSEC_VENDORID_INTEL 0x8086 > +#define INTEL_PCI_DVSEC_DVSECID_MEASUREMENT 0x3E > + > +/// > +/// The Intel PCI digest modified macro. > +/// > +#define INTEL_PCI_DIGEST_MODIFIED BIT0 > + > +/// > +/// The Intel PCI DVSEC digest data modified structure. > +/// > +typedef union { > + struct { > + UINT8 DigestModified:1; // RW1C > + UINT8 Reserved0:7; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_MODIFIED; > + > +/// > +/// The Intel PCI digest valid macro. > +/// > +#define INTEL_PCI_DIGEST_0_VALID BIT0 > +#define INTEL_PCI_DIGEST_0_LOCKED BIT1 > +#define INTEL_PCI_DIGEST_1_VALID BIT2 > +#define INTEL_PCI_DIGEST_1_LOCKED BIT3 > + > +/// > +/// The Intel PCI DVSEC digest data valid structure. > +/// > +typedef union { > + struct { > + UINT8 Digest0Valid:1; // RO > + UINT8 Digest0Locked:1; // RO > + UINT8 Digest1Valid:1; // RO > + UINT8 Digest1Locked:1; // RO > + UINT8 Reserved1:4; > + } Bits; > + UINT8 Data; > +} INTEL_PCI_DIGEST_DATA_VALID; > + > +/// > +/// The PCIE capability structure for Intel PCI DVSEC extension with dig= est. > +/// > +typedef struct { > + INTEL_PCI_DIGEST_DATA_MODIFIED Modified; // RW1C > + INTEL_PCI_DIGEST_DATA_VALID Valid; // RO > + UINT16 TcgAlgId; // RO > + UINT8 FirmwareID; // RO > + UINT8 Reserved; > +//UINT8 Digest[]; > +} INTEL_PCI_DIGEST_CAPABILITY_STRUCTURE; > + > +#pragma pack() > + > +#endif > + > -- > 2.19.2.windows.1