From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.3362.1576133669344219112 for ; Wed, 11 Dec 2019 22:54:29 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2019 22:54:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,304,1571727600"; d="scan'208";a="415138305" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga006.fm.intel.com with ESMTP; 11 Dec 2019 22:54:28 -0800 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 22:54:27 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 22:54:27 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.90]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.214]) with mapi id 14.03.0439.000; Thu, 12 Dec 2019 14:54:25 +0800 From: "Ni, Ray" To: Tom Lendacky , "devel@edk2.groups.io" CC: "Justen, Jordan L" , Laszlo Ersek , Ard Biesheuvel , "Kinney, Michael D" , "Gao, Liming" , "Dong, Eric" , Brijesh Singh Subject: Re: [RFC PATCH v3 28/43] OvmfPkg: Create GHCB pages for use during Pei and Dxe phase Thread-Topic: [RFC PATCH v3 28/43] OvmfPkg: Create GHCB pages for use during Pei and Dxe phase Thread-Index: AQHVn95BhsgMhYb6Q0SvNgFvJxuCL6e2MYtg Date: Thu, 12 Dec 2019 06:54:25 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C399A65@SHSMSX104.ccr.corp.intel.com> References: <274fae2f1eb0e6036dd893c621f3c89b906db8d9.1574280425.git.thomas.lendacky@amd.com> In-Reply-To: <274fae2f1eb0e6036dd893c621f3c89b906db8d9.1574280425.git.thomas.lendacky@amd.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjM4Y2Y2MTctMWQxYi00OWZjLTk2OTAtZTk1ZDQ4NDRkYjk5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoic0hLcGpURG40Nmg2SHRTM0ROelwvXC9QSEg2U0N0MVJcLzBkbDdqSzZyVnV2YnAwNmU0aGoraFBKVU14RjRWRE1SWCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > + // Allocate GHCB and per-CPU variable pages. > + // > + GhcbPageCount =3D mMaxCpuCount * 2; > + GhcbBase =3D AllocatePages (GhcbPageCount); > + ASSERT (GhcbBase !=3D NULL); > + > + GhcbBasePa =3D (PHYSICAL_ADDRESS)(UINTN) GhcbBase; > + > + DecryptStatus =3D MemEncryptSevClearPageEncMask ( > + 0, > + GhcbBasePa, > + GhcbPageCount, > + TRUE > + ); > + ASSERT_RETURN_ERROR (DecryptStatus); > + > + ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount)); > + > + PcdStatus =3D PcdSet64S (PcdGhcbBase, GhcbBasePa); > + ASSERT_RETURN_ERROR (PcdStatus); > + PcdStatus =3D PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount= )); > + ASSERT_RETURN_ERROR (PcdStatus); > + > + DEBUG ((DEBUG_INFO, > + "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n", > + (UINT64)GhcbPageCount, GhcbBase)); > + > + AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); As I said in the comments to PcdGhcbBase/Size, can all PCD consumers read t= he GHCB MSR instead? Does the GHCB buffer contains size information? If no, how does CPU know th= e GHCB buffer size? I am asking this because I want to see a way to remove the PcdGhcbSize. Thanks, Ray