From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.4917.1576721692761456395 for ; Wed, 18 Dec 2019 18:14:52 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2019 18:14:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,330,1571727600"; d="scan'208";a="218339478" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 18 Dec 2019 18:14:52 -0800 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 18 Dec 2019 18:14:51 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 18 Dec 2019 18:14:51 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.90]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.46]) with mapi id 14.03.0439.000; Thu, 19 Dec 2019 10:14:49 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "'devel@edk2.groups.io'" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Thread-Index: AQHVmdK5Hh4LyD94NUChTjCCT7Tp3Ke+eYzQgAFXgdD//9X+AIABSCNA Date: Thu, 19 Dec 2019 02:14:49 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3A26DC@SHSMSX104.ccr.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127D273722D4.32624@groups.io> <95C5C2B113DE604FB208120C742E9824579172AC@BGSMSX101.gar.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C3A189E@SHSMSX104.ccr.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C3A19C4@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E98245797C412@BGSMSX101.gar.corp.intel.com> In-Reply-To: <95C5C2B113DE604FB208120C742E98245797C412@BGSMSX101.gar.corp.intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ashraf, At the end of PciFeatureGetDevicePolicy, value from the PCI features confi= guration table is the minimum one. I prefer to defer the finalize of PciDevice->SetupMPS in the OverrideMaxPa= yloadSize(). Through this, the 4 phases can be reduced to 3 phases. Thanks, Ray > -----Original Message----- > From: Javeed, Ashraf > Sent: Wednesday, December 18, 2019 10:36 PM > To: Ni, Ray ; 'devel@edk2.groups.io' > > Cc: Wang, Jian J ; Wu, Hao A > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] > PciBusDxe: New PCI feature Max_Payload_Size >=20 > Ray, > As discussed, the ProcessMaxPayloadSize() gets the minimum payload size > for all devices under a certain root port, at the end of PciFeatureSetup= Phase. > The value from the PCI features configuration table is aligned to each o= f > PciDevice->SetupMPS, under a root port. > The PciDevice->SetupMPS is used for its corresponding device's > MaxReadRequestSize feature conditionally, since there is no PCIe capabil= ity > for this feature. > Thus, as per the implementation design formulated here, all the PciDevic= e- > >SetupXXX has to be finalized, considering the device policy, during the > phases - PciFeatureGetDevicePolicy & PciFeatureSetupPhase. Finally, it s= hall > be programmed during the phase PciFeatureConfigurationPhase. > The OverrideMaxPayloadSize() does not have to use the PCI features > configuration table, as that table is temporarily meant for aligning a f= eature > value among all devices of a root port. >=20 > Responding to your other comments below inline. > Thanks > Ashraf >=20 >=20 > > -----Original Message----- > > From: Ni, Ray > > Sent: Wednesday, December 18, 2019 2:40 PM > > To: Javeed, Ashraf ; 'devel@edk2.groups.io' > > > > Cc: Wang, Jian J ; Wu, Hao A > > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > 08/12] > > PciBusDxe: New PCI feature Max_Payload_Size > > > > Ashraf, > > Can ProcessMaxPayloadSize() get the minimum payload size for all devic= es > under > > a certain root port? > > > > I can understand that the payload size stored in the PCI features > configuration > > table is the minimum value. > > But the value stored in each PciDevice->SetupMPS is not the minimum > value. > > > > So OverrideMaxPayloadSize() should use the value stored in the PCI > features > > configuration table instead of the value stored in PciDevice->SetupMPS= . > > > > Thanks, > > Ray > > > > > -----Original Message----- > > > From: Ni, Ray > > > Sent: Wednesday, December 18, 2019 4:38 PM > > > To: Javeed, Ashraf ; devel@edk2.groups.io > > > Cc: Wang, Jian J ; Wu, Hao A > > > > > > Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH > > > 08/12] PciBusDxe: New PCI feature Max_Payload_Size > > > > > > > > + UINT8 SetupMPS; > > > 1. Can it be "MaxPayloadSize"? > I thought prefixing the name with "Setup" can imply that this data membe= r > of PCI_IO_DEVICE would help to indicate it takes the device policy, > transforms into the final raw value after calculation, which shall be > programmed in to hardware control register. I have used same style for a= ll > other features, and I have to rename all those....I don't see any confli= ct in the > name SetupMPS as we know that MPS is shorthand for the > MaxPayLoadSize... >=20 > > > > > + > > > > > + if (PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { > > > > > + if (SetupMpsAsPerDeviceCapability (PciDevice->SetupMPS)) { > > > > > > 2. Can you replace " SetupMpsAsPerDeviceCapability > > > (PciDevice->SetupMPS" with "PciDevice->MaxPayloadSize =3D=3D > > EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO"? > > > This makes the code more readable. > > > > I thought the routine name itself informally indicate what type of actio= n it has > to take based on *_AUTO EFI encoding....I shall reconsider this. >=20 > > > > > + MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; > > > > > + // > > > > > + // no change to PCI Root ports without any endpoint devic= e > > > > > + // > > > > > + if (IS_PCI_BRIDGE (&PciDevice->Pci) && > > > > > + PciDeviceCap.Bits.MaxPayloadSize) > > > > > { > > > > > + if (IsPciRootPortEmpty (PciDevice)) { > > > > > + MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > + } > > > > > + } > > > > > > 3. Above two if-s can be simplified as below? and please also copy t= he > spec > > requirements here as comments. > > > if (IsListEmpty (&PciDevice->ChildList)) { > > > MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; } > > > > OK >=20 > > > > > > > > > > > + } else { > > > > > + MpsValue =3D TranslateMpsSetupValueToPci > > > > > + (PciDevice->SetupMPS); > > > > > > 4. The function name can be "UefiToPciMaxPayloadSize()". And I sugge= st > > > the value stored in PciDevice->SetupMPS (MaxPayloadSize) is the macr= o > > > value defined in PciExpress21.h. We could do the conversion just aft= er > the > > GetDevicePolicy() call. > > > > Ok, I can rename to the suggested name for the translation routine. But,= I > cannot use that immediately after the GetDevicePolicy() because some of > the PCIe features are defined in the capability register and its *_AUTO = can be > used in co-relation to that; like in case of MaxPayloadSize feature; but= in case > of PCIe feature like RelaxOrdering & NoSnoop, the PCI Base Specification= has > not defined any corresponding capability or hardware reference value for > look-up, thus *_AUTO for these kind of features would be to just ignore = it. >=20 > > > > > + } > > > > > + // > > > > > + // discard device policy override request if greater than P= CI device > > capability > > > > > + // > > > > > + PciDevice->SetupMPS =3D MIN > > > > > + ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, > > > > > + MpsValue); } > > > > > + > > > > > + // > > > > > + // align the MPS of the tree to the HCF with this device // > > > > > + if > > > > > + (PciFeaturesConfigurationTable) { > > > > > + MpsValue =3D PciFeaturesConfigurationTable->Max_Payload_Siz= e; > > > > > > 5. Max_Payload_Size can be "MaxPayloadSize". > > > MpsValue can be "MaxPayloadSize". > > > > OK >=20 > > > > > + > > > > > + MpsValue =3D MIN (PciDevice->SetupMPS, MpsValue); > > > > > + PciDevice->SetupMPS =3D MIN (PciDevice->SetupMPS, MpsValue)= ; > > > > > + > > > > > + if (MpsValue !=3D PciFeaturesConfigurationTable- > >Max_Payload_Size) { > > > > > + PciFeaturesConfigurationTable->Max_Payload_Size =3D MpsVa= lue; > > > > > + } > > > > > + } > > > > > > 6. Can you simplify the above logic? > > > > Will check on this >=20 > > > > > + > > > > > + DEBUG (( DEBUG_INFO, > > > > > + "MPS: %d [DevCap:%d],", > > > > > + PciDevice->SetupMPS, PciDeviceCap.Bits.MaxPayloadSize > > > > > + )); > > > > > + return EFI_SUCCESS; > > > > > +} > > > > > + > > > > > +/** > > > > > + Overrides the PCI Device Control register MaxPayloadSize > > > > > +register field; if > > > > > + the hardware value is different than the intended value. > > > > > + > > > > > + @param PciDevice A pointer to the PCI_IO_DEVICE = instance. > > > > > + > > > > > + @retval EFI_SUCCESS The data was read from or writt= en to the > PCI > > > > > device. > > > > > + @retval EFI_UNSUPPORTED The address range specified by > Offset, > > Width, > > > > > and Count is not > > > > > + valid for the PCI configuration= header of the PCI > > controller. > > > > > + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is inva= lid. > > > > > + > > > > > +**/ > > > > > +EFI_STATUS > > > > > +OverrideMaxPayloadSize ( > > > > > + IN PCI_IO_DEVICE *PciDevice > > > > > + ) > > > > > > 7. Can this name be "ProgramMaxPayloadSize" because the function > does > > > the register programming? > > > > OK >=20 > > > > > +{ > > > > > + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; > > > > > + UINT32 Offset; > > > > > + EFI_STATUS Status; > > > > > + EFI_TPL OldTpl; > > > > > + > > > > > + PcieDev.Uint16 =3D 0; > > > > > + Offset =3D PciDevice->PciExpressCapabilityOffset + > > > > > + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl)= ; > > > > > + Status =3D PciDevice->PciIo.Pci.Read ( > > > > > + &PciDevice->PciIo, > > > > > + EfiPciIoWidthUint16, > > > > > + Offset, > > > > > + 1, > > > > > + &PcieDev.Uint16 > > > > > + ); > > > > > > 8. The PciExp is cached in PciExp field in the PciDevice structure. > > > Why do you need to read it from HW again? > > > > Just for the sake of defensive programming; in case platform has done so= me > overrides in between; since numerous callbacks are going to platform cod= e > of PCI Host Bridge Resource Allocation Protocol driver, and PCI Platfor= m > Protocol driver. >=20 > > > > > + if (EFI_ERROR(Status)){ > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > > > > + (0x%x) read > > > > > error!", > > > > > + Offset > > > > > + )); > > > > > + return Status; > > > > > + } > > > > > + if (PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) { > > > > > + PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS; > > > > > + DEBUG (( DEBUG_INFO, "MPS=3D%d,", PciDevice->SetupMPS)); > > > > > + > > > > > + // > > > > > + // Raise TPL to high level to disable timer interrupt while > > > > > + the write operation > > > > > completes > > > > > + // > > > > > + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); > > > > > + > > > > > + Status =3D PciDevice->PciIo.Pci.Write ( > > > > > + &PciDevice->PciIo, > > > > > + EfiPciIoWidthUint16, > > > > > + Offset, > > > > > + 1, > > > > > + &PcieDev.Uint16 > > > > > + ); > > > > > + // > > > > > + // Restore TPL to its original level > > > > > + // > > > > > + gBS->RestoreTPL (OldTpl); > > > > > + > > > > > + if (!EFI_ERROR(Status)) { > > > > > + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.= Uint16; > > > > > + } else { > > > > > + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register > > > > > + (0x%x) write > > > > > error!", > > > > > + Offset > > > > > + )); > > > > > > 9. We can use ASSERT_EFI_ERROR() here. Failure of register writing i= s a > fatal > > error. > > > > OK >=20 > > > > > + } > > > > > + } else { > > > > > + DEBUG (( DEBUG_INFO, "No write of MPS=3D%d,", > > > > > + PciDevice->SetupMPS)); > > > > > > 10. Can we skip this debug message? > > > > OK >=20 > > > > > + } > > > > > + > > > > > + return Status; > > > > > +} > > > > > > > > > > /** > > > > > helper routine to dump the PCIe Device Port Type @@ -669,6 > > > > > +809,18 @@ SetupDevicePciFeatures ( > > > > > } > > > > > } > > > > > > > > > > + DEBUG ((DEBUG_INFO, "[")); > > > > > + // > > > > > + // process the PCI device Max_Payload_Size feature // if > > > > > + (SetupMaxPayloadSize ()) { > > > > > + Status =3D ProcessMaxPayloadSize ( > > > > > + PciDevice, > > > > > + PciConfigPhase, > > > > > + OtherPciFeaturesConfigTable > > > > > + ); > > > > > > 11. Can this function be "CalculatemaxPayloadSize"? Process is too > general. > > > > OK >=20 > > > > > + } > > > > > + DEBUG ((DEBUG_INFO, "]\n")); > > > > > return Status; > > > > > } > > > > > > > > > > @@ -765,6 +917,10 @@ ProgramDevicePciFeatures ( { > > > > > EFI_STATUS Status =3D EFI_SUCCESS; > > > > > > > > > > + if (SetupMaxPayloadSize ()) { > > > > > + Status =3D OverrideMaxPayloadSize (PciDevice); } DEBUG (( > > > > > + DEBUG_INFO, "\n")); > > > > > return Status; > > > > > } > > > > > > > > > > @@ -878,6 +1034,7 @@ AddPrimaryRootPortNode ( > > > > > ); > > > > > if (PciConfigTable) { > > > > > PciConfigTable->ID =3D PortNumber; > > > > > + PciConfigTable->Max_Payload_Size =3D > > > > > PCIE_MAX_PAYLOAD_SIZE_4096B; > > > > > } > > > > > RootPortNode->OtherPciFeaturesConfigurationTable =3D > > > > > PciConfigTable; > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > index f92d008..e5ac2a3 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > > > > > @@ -79,6 +79,11 @@ struct > > _OTHER_PCI_FEATURES_CONFIGURATION_TABLE > > > > > { > > > > > // Configuration Table ID > > > > > // > > > > > UINTN ID; > > > > > + // > > > > > + // to configure the PCI feature Maximum payload size to > > > > > + maintain the data packet // size among all the PCI devices in > > > > > + the PCI hierarchy // > > > > > + UINT8 Max_Payload_Size; > > > > > }; > > > > > > > > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > index 238959e..99badd6 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > > > > > @@ -356,6 +356,63 @@ GetPlatformPciOptionRom ( > > > > > return Status; > > > > > } > > > > > > > > > > +/** > > > > > + Helper routine to indicate whether the given PCI device > > > > > +specific policy value > > > > > + dictates to override the Max_Payload_Size to a particular > > > > > +value, or set as per > > > > > + device capability. > > > > > + > > > > > + @param MPS Input device-specific policy should be in ter= ms of > type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > + > > > > > + @retval TRUE Setup Max_Payload_Size as per device capabili= ty > > > > > + FALSE override as per device-specific platform poli= cy > > > > > +**/ > > > > > +BOOLEAN > > > > > +SetupMpsAsPerDeviceCapability ( > > > > > + IN UINT8 MPS > > > > > +) > > > > > +{ > > > > > + if (MPS =3D=3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO) { > > > > > + return TRUE; > > > > > + } else { > > > > > + return FALSE; > > > > > + } > > > > > +} > > > > > + > > > > > +/** > > > > > + Routine to translate the given device-specific platform polic= y > > > > > +from type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per > PCI > > > > > +Base Specification > > > > > + Revision 4.0; for the PCI feature Max_Payload_Size. > > > > > + > > > > > + @param MPS Input device-specific policy should be in ter= ms of > type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > + > > > > > + @retval Range values for the Max_Payload_Size as defi= ned in > the > > PCI > > > > > + Base Specification 4.0 **/ > > > > > +UINT8 > > > > > +TranslateMpsSetupValueToPci ( > > > > > + IN UINT8 MPS > > > > > +) > > > > > +{ > > > > > + switch (MPS) { > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_128B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_256B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_256B; > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_512B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_512B; > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_1024B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_1024B; > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_2048B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_2048B; > > > > > + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_4096B: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_4096B; > > > > > + default: > > > > > + return PCIE_MAX_PAYLOAD_SIZE_128B; > > > > > + } > > > > > +} > > > > > + > > > > > /** > > > > > Generic routine to setup the PCI features as per its predeter= mined > > defaults. > > > > > **/ > > > > > @@ -364,6 +421,7 @@ SetupDefaultsDevicePlatformPolicy ( > > > > > IN PCI_IO_DEVICE *PciDevice > > > > > ) > > > > > { > > > > > + PciDevice->SetupMPS =3D > EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; > > > > > } > > > > > > > > > > /** > > > > > @@ -399,6 +457,7 @@ GetPciDevicePlatformPolicyEx ( > > > > > // > > > > > // platform chipset policies are returned for this PCI de= vice > > > > > // > > > > > + PciIoDevice->SetupMPS =3D > > > > > + PciPlatformExtendedPolicy.DeviceCtlMPS; > > > > > > > > > > DEBUG (( > > > > > DEBUG_INFO, "[device policy: platform]" > > > > > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > index a13131c..786c00d 100644 > > > > > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > > > > > @@ -124,4 +124,36 @@ EFI_STATUS > > > > > GetPciDevicePlatformPolicy ( > > > > > IN PCI_IO_DEVICE *PciDevice > > > > > ); > > > > > + > > > > > +/** > > > > > + Helper routine to indicate whether the given PCI device > > > > > +specific policy value > > > > > + dictates to override the Max_Payload_Size to a particular > > > > > +value, or set as per > > > > > + device capability. > > > > > + > > > > > + @param MPS Input device-specific policy should be in ter= ms of > type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > + > > > > > + @retval TRUE Setup Max_Payload_Size as per device capabili= ty > > > > > + FALSE override as per device-specific platform poli= cy > > > > > +**/ > > > > > +BOOLEAN > > > > > +SetupMpsAsPerDeviceCapability ( > > > > > + IN UINT8 MPS > > > > > +); > > > > > + > > > > > +/** > > > > > + Routine to translate the given device-specific platform polic= y > > > > > +from type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per > PCI > > > > > +Base Specification > > > > > + Revision 4.0; for the PCI feature Max_Payload_Size. > > > > > + > > > > > + @param MPS Input device-specific policy should be in ter= ms of > type > > > > > + EFI_PCI_CONF_MAX_PAYLOAD_SIZE > > > > > + > > > > > + @retval Range values for the Max_Payload_Size as defi= ned in > the > > PCI > > > > > + Base Specification 4.0 **/ > > > > > +UINT8 > > > > > +TranslateMpsSetupValueToPci ( > > > > > + IN UINT8 MPS > > > > > +); > > > > > #endif > > > > > -- > > > > > 2.21.0.windows.1 > > > > > > > > > > > > > > >=20