From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.1314.1577159307932993874 for ; Mon, 23 Dec 2019 19:48:28 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Dec 2019 19:48:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,350,1571727600"; d="scan'208";a="268316315" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 23 Dec 2019 19:48:27 -0800 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 23 Dec 2019 19:48:27 -0800 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 23 Dec 2019 19:48:26 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 23 Dec 2019 19:48:26 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.90]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.222]) with mapi id 14.03.0439.000; Tue, 24 Dec 2019 11:48:25 +0800 From: "Ni, Ray" To: "Wu, Hao A" , "devel@edk2.groups.io" CC: "Dong, Eric" , Laszlo Ersek , "Zeng, Star" , "Fu, Siyuan" , "Kinney, Michael D" Subject: Re: [PATCH v1 3/4] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Thread-Topic: [PATCH v1 3/4] UefiCpuPkg: Add definitions for EDKII microcode patch HOB Thread-Index: AQHVufqnPubl/690IECz+4u7o6hnZKfIooFg Date: Tue, 24 Dec 2019 03:48:24 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3A9E97@SHSMSX104.ccr.corp.intel.com> References: <20191224013656.13404-1-hao.a.wu@intel.com> <20191224013656.13404-4-hao.a.wu@intel.com> In-Reply-To: <20191224013656.13404-4-hao.a.wu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > + // > + // The number of processors within the system. > + // > + UINT32 ProcessorNumber; 1. Number is a bit confusing here. I also provided comments to other patche= s. We could "ProcessorCount" here. Number can be either count of items, or an index to a specific item. > + // > + // An array with 'ProcessorNumber' elements that stores the offset (wi= th > + // regard to 'MicrocodePatchAddress') of the applied microcode patch f= or > each > + // processor. > + // If no microcode patch is applied for certain processor, the relatin= g > + // element will be set to MAX_UINT64. > + // > + UINT64 DetectedPatchOffset[0]; 2. "ProcessorSpecificPatchOffset"?