From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.11065.1577263942816215764 for ; Wed, 25 Dec 2019 00:52:24 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Dec 2019 00:52:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,353,1571727600"; d="scan'208";a="417758975" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 25 Dec 2019 00:52:22 -0800 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Dec 2019 00:52:21 -0800 Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 25 Dec 2019 00:52:21 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 25 Dec 2019 00:52:21 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.90]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.46]) with mapi id 14.03.0439.000; Wed, 25 Dec 2019 16:52:19 +0800 From: "Ni, Ray" To: "Wu, Hao A" , "devel@edk2.groups.io" CC: "Dong, Eric" , Laszlo Ersek , "Zeng, Star" , "Fu, Siyuan" , "Kinney, Michael D" Subject: Re: [PATCH v2 5/6] UefiCpuPkg/MpInitLib: Relocate microcode patch fields in CPU_MP_DATA Thread-Topic: [PATCH v2 5/6] UefiCpuPkg/MpInitLib: Relocate microcode patch fields in CPU_MP_DATA Thread-Index: AQHVuvkX5o80dmPN8kWkJkLhj7YUaKfKimIA Date: Wed, 25 Dec 2019 08:52:19 +0000 Deferred-Delivery: Wed, 25 Dec 2019 08:50:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3AADE3@SHSMSX104.ccr.corp.intel.com> References: <20191225075814.8372-1-hao.a.wu@intel.com> <20191225075814.8372-6-hao.a.wu@intel.com> In-Reply-To: <20191225075814.8372-6-hao.a.wu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Wu, Hao A > Sent: Wednesday, December 25, 2019 3:58 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Dong, Eric ; Ni, > Ray ; Laszlo Ersek ; Zeng, Star > ; Fu, Siyuan ; Kinney, Michael > D > Subject: [PATCH v2 5/6] UefiCpuPkg/MpInitLib: Relocate microcode patch > fields in CPU_MP_DATA >=20 > The below 2 microcode patch related fields in structure CPU_MP_DATA: >=20 > UINT64 MicrocodePatchAddress; > UINT64 MicrocodePatchRegionSize; >=20 > They will be passed from PEI phase and be reused DXE phase. >=20 > Previously, these 2 fields were placed after some fields with type > 'UINTN', this will lead to different field offset in different > architecture for them. >=20 > This commit will move them before the fields with different size in > different architecture to ensure they can be properly used in DXE phase. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Star Zeng > Cc: Siyuan Fu > Cc: Michael D Kinney > Signed-off-by: Hao A Wu > --- > UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 885656900c..5f50e79744 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -217,6 +217,8 @@ struct _CPU_MP_DATA { > UINT64 CpuInfoInHob; > UINT32 CpuCount; > UINT32 BspNumber; > + UINT64 MicrocodePatchAddress; > + UINT64 MicrocodePatchRegionSize; > // > // The above fields data will be passed from PEI to DXE > // Please make sure the fields offset same in the different > @@ -260,8 +262,6 @@ struct _CPU_MP_DATA { > UINT8 Vector; > BOOLEAN PeriodicMode; > BOOLEAN TimerInterruptState; > - UINT64 MicrocodePatchAddress; > - UINT64 MicrocodePatchRegionSize; >=20 > UINT32 ProcessorSignature; > UINT32 ProcessorFlags; > -- > 2.12.0.windows.1