From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web11.950.1578366248697291826 for ; Mon, 06 Jan 2020 19:04:08 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jan 2020 19:04:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,404,1571727600"; d="scan'208";a="215395217" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga008.jf.intel.com with ESMTP; 06 Jan 2020 19:04:08 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 6 Jan 2020 19:04:07 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 6 Jan 2020 19:04:07 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.197]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.139]) with mapi id 14.03.0439.000; Tue, 7 Jan 2020 11:04:05 +0800 From: "Ni, Ray" To: "Fu, Siyuan" , "devel@edk2.groups.io" CC: "Dong, Eric" , "Wu, Hao A" Subject: Re: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when calculate microcode patch size. Thread-Topic: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when calculate microcode patch size. Thread-Index: AQHVwgVrwTw64pF3EUCiQSTnRRd3LafeibwQ Date: Tue, 7 Jan 2020 03:04:05 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3DBE4E@SHSMSX104.ccr.corp.intel.com> References: <20200103071411.10760-1-siyuan.fu@intel.com> In-Reply-To: <20200103071411.10760-1-siyuan.fu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Fu, Siyuan > Sent: Friday, January 3, 2020 3:14 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Wu, Hao= A > > Subject: [Patch 1/1] UefiCpuPkg: Remove redundant alignment check when > calculate microcode patch size. >=20 > This patch removes the unnecessary alignment check on microcode patch > TotalSize > introduced by commit d786a172. The TotalSize has already been checked > with 1K > alignment and MAX_ADDRESS in previous code as below: >=20 > if ( (UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize) || > ((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd || > (DataSize & 0x3) !=3D 0 || > (TotalSize & (SIZE_1KB - 1)) !=3D 0 || > TotalSize < DataSize > ) { >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Hao A Wu > Signed-off-by: Siyuan Fu > --- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 24 +++++------------------- > UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +-- > 2 files changed, 6 insertions(+), 21 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c > b/UefiCpuPkg/Library/MpInitLib/Microcode.c > index 3da5bfb9cf2f..a9d06dd4099a 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -1,7 +1,7 @@ > /** @file > Implementation of loading microcode on processors. >=20 > - Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -397,16 +397,7 @@ LoadMicrocodePatchWorker ( > Patches[Index].Size > ); >=20 > - // > - // Zero-fill the padding area > - // Please note that AlignedSize will be no less than Size > - // > - ZeroMem ( > - Walker + Patches[Index].Size, > - Patches[Index].AlignedSize - Patches[Index].Size > - ); > - > - Walker +=3D Patches[Index].AlignedSize; > + Walker +=3D Patches[Index].Size; > } >=20 > // > @@ -578,14 +569,9 @@ LoadMicrocodePatch ( > // > // Store the information of this microcode patch > // > - if (TotalSize > ALIGN_VALUE (TotalSize, SIZE_1KB) || > - ALIGN_VALUE (TotalSize, SIZE_1KB) > MAX_UINTN - TotalLoadSize)= { > - goto OnExit; > - } > - PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) > MicrocodeEntryPoint; > - PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > - PatchInfoBuffer[PatchCount - 1].AlignedSize =3D ALIGN_VALUE (Total= Size, > SIZE_1KB); > - TotalLoadSize +=3D PatchInfoBuffer[PatchCount - 1].AlignedSize; > + PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) > MicrocodeEntryPoint; > + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > + TotalLoadSize +=3D TotalSize; > } >=20 > // > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 6609c958ce8a..b6e5a1afab00 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -1,7 +1,7 @@ > /** @file > Common header file for MP Initialize Library. >=20 > - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -54,7 +54,6 @@ > typedef struct { > UINTN Address; > UINTN Size; > - UINTN AlignedSize; > } MICROCODE_PATCH_INFO; >=20 > // > -- > 2.19.1.windows.1