From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8319.1578492746333809883 for ; Wed, 08 Jan 2020 06:12:26 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jan 2020 06:12:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,410,1571727600"; d="scan'208";a="222940767" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga006.jf.intel.com with ESMTP; 08 Jan 2020 06:12:25 -0800 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 8 Jan 2020 06:12:25 -0800 Received: from fmsmsx609.amr.corp.intel.com (10.18.126.89) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 8 Jan 2020 06:12:24 -0800 Received: from shsmsx107.ccr.corp.intel.com (10.239.4.96) by fmsmsx609.amr.corp.intel.com (10.18.126.89) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 8 Jan 2020 06:12:24 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.197]) by SHSMSX107.ccr.corp.intel.com ([169.254.9.210]) with mapi id 14.03.0439.000; Wed, 8 Jan 2020 22:12:22 +0800 From: "Ni, Ray" To: "Gao, Liming" , "devel@edk2.groups.io" CC: "Voelz, Jason" Subject: Re: [Patch 2/2] UefiCpuPkg/CpuCommonFeaturesLib: SMXE bit of CR4 should set Thread-Topic: [Patch 2/2] UefiCpuPkg/CpuCommonFeaturesLib: SMXE bit of CR4 should set Thread-Index: AQHVuV4NnKRAgk9K6EeC3gihOh021Kfg6FKQ Date: Wed, 8 Jan 2020 14:12:21 +0000 Deferred-Delivery: Wed, 8 Jan 2020 14:12:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3E0248@SHSMSX104.ccr.corp.intel.com> References: <20191223065537.32468-1-liming.gao@intel.com> <20191223065537.32468-3-liming.gao@intel.com> In-Reply-To: <20191223065537.32468-3-liming.gao@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Gao, Liming > Sent: Monday, December 23, 2019 2:56 PM > To: devel@edk2.groups.io > Cc: Voelz, Jason ; Ni, Ray > Subject: [Patch 2/2] UefiCpuPkg/CpuCommonFeaturesLib: SMXE bit of CR4 sho= uld set >=20 > From: Jason Voelz >=20 > Add code to set SMXE in CR4 in the SmxInitialize flow when SMX is enabled= . >=20 > Signed-off-by: Jason Voelz > Cc: Ray Ni > --- > UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c | 9 +++++++++ > 1 file changed, 9 insertions(+) >=20 > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c > index 38d3f53f56..b4474d2fab 100644 > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c > @@ -240,6 +240,15 @@ SmxInitialize ( > Status =3D RETURN_UNSUPPORTED; > } >=20 > + CPU_REGISTER_TABLE_WRITE_FIELD ( > + ProcessorNumber, > + ControlRegister, > + 4, > + IA32_CR4, > + Bits.SMXE, > + (State) ? 1 : 0 > + ) > + > CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( > ProcessorNumber, > Msr, > -- > 2.13.0.windows.1