From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web12.10100.1578664281986078536 for ; Fri, 10 Jan 2020 05:51:22 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2020 05:51:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,417,1571727600"; d="scan'208";a="247036090" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 10 Jan 2020 05:51:21 -0800 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 10 Jan 2020 05:51:21 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 10 Jan 2020 05:51:20 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.197]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.55]) with mapi id 14.03.0439.000; Fri, 10 Jan 2020 21:51:18 +0800 From: "Ni, Ray" To: "Fu, Siyuan" , "devel@edk2.groups.io" CC: "Dong, Eric" , Laszlo Ersek Subject: Re: [Patch] UefiCpuPkg: Add microcode flash address to EDKII microcode patch HOB. Thread-Topic: [Patch] UefiCpuPkg: Add microcode flash address to EDKII microcode patch HOB. Thread-Index: AQHVx4S/lV6tdGKHm0KsHwasGeWBaafj6ovw Date: Fri, 10 Jan 2020 13:51:18 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C3E8CB7@SHSMSX104.ccr.corp.intel.com> References: <33c518f2a59d52a9c78bf1ed3f96eb5e0195a5ba.1578639982.git.siyuan.fu@intel.com> In-Reply-To: <33c518f2a59d52a9c78bf1ed3f96eb5e0195a5ba.1578639982.git.siyuan.fu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I will review next Monday. > -----Original Message----- > From: Fu, Siyuan > Sent: Friday, January 10, 2020 3:08 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Laszlo = Ersek > > Subject: [Patch] UefiCpuPkg: Add microcode flash address to EDKII microco= de > patch HOB. >=20 > This patch adds the original microcode flash address to EDKII microcode > patch HOB after the microcode loaded by processor. This information can > be used to check if a microcode slot has been used by existing processor > or not. >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2454 >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Signed-off-by: Siyuan Fu > --- > UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 12 ++++- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 24 +++++---- > UefiCpuPkg/Library/MpInitLib/MpLib.h | 9 ++++ > UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 54 +++++++++++++++++++-- > 4 files changed, 84 insertions(+), 15 deletions(-) >=20 > diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > index 2d307fbffb..bbf6f2c66b 100644 > --- a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h > @@ -3,7 +3,7 @@ > A. Base address and size of the loaded microcode patches data; > B. Detected microcode patch for each processor within system. >=20 > - Copyright (c) 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -38,7 +38,15 @@ typedef struct { > // If no microcode patch is detected for certain processor, the relati= ng > // element will be set to MAX_UINT64. > // > - UINT64 ProcessorSpecificPatchOffset[0]; > + //UINT64 ProcessorSpecificPatchOffset[]; > + // > + // An array with 'ProcessorCount' elements that stores the original > + // microcode patch address in flash if the patch has been shadowed to > + // memory. This address will be the same one as specified by > + // "MicrocodePatchAddress" with "PatchOffset" if the patch wasn't > + // shadowed to memory. > + // > + //UINT64 ProcessorSpecificPatchAddrInRom[]; > } EDKII_MICROCODE_PATCH_HOB; >=20 > #endif > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c > b/UefiCpuPkg/Library/MpInitLib/Microcode.c > index 9389e52ae5..3af5b8495f 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -460,6 +460,7 @@ ShadowMicrocodePatchWorker ( > (VOID *) Patches[Index].Address, > Patches[Index].Size > ); > + Patches[Index].AddressInRam =3D (UINTN) Walker; > Walker +=3D Patches[Index].Size; > } >=20 > @@ -519,7 +520,7 @@ ShadowMicrocodePatchByPcd ( > PatchCount =3D 0; > MaxPatchNumber =3D DEFAULT_MAX_MICROCODE_PATCH_NUM; > TotalLoadSize =3D 0; > - PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof > (MICROCODE_PATCH_INFO)); > + PatchInfoBuffer =3D AllocateZeroPool (MaxPatchNumber * sizeof > (MICROCODE_PATCH_INFO)); > if (PatchInfoBuffer =3D=3D NULL) { > return; > } > @@ -563,7 +564,7 @@ ShadowMicrocodePatchByPcd ( > // > // Overflow check for MaxPatchNumber > // > - goto OnExit; > + goto OnError; > } >=20 > PatchInfoBuffer =3D ReallocatePool ( > @@ -572,7 +573,7 @@ ShadowMicrocodePatchByPcd ( > PatchInfoBuffer > ); > if (PatchInfoBuffer =3D=3D NULL) { > - goto OnExit; > + goto OnError; > } > MaxPatchNumber =3D MaxPatchNumber * 2; > } > @@ -581,7 +582,7 @@ ShadowMicrocodePatchByPcd ( > // Store the information of this microcode patch > // > PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) MicrocodeEntry= Point; > - PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; > TotalLoadSize +=3D TotalSize; > } >=20 > @@ -601,7 +602,11 @@ ShadowMicrocodePatchByPcd ( > ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, > TotalLoadSize); > } >=20 > -OnExit: > + CpuMpData->PatchCount =3D PatchCount; > + CpuMpData->PatchInfoBuffer =3D PatchInfoBuffer; > + return; > + > +OnError: > if (PatchInfoBuffer !=3D NULL) { > FreePool (PatchInfoBuffer); > } > @@ -674,7 +679,7 @@ ShadowMicrocodePatchByFit ( > return EFI_NOT_FOUND; > } >=20 > - PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof > (MICROCODE_PATCH_INFO)); > + PatchInfoBuffer =3D AllocateZeroPool (MaxPatchNumber * sizeof > (MICROCODE_PATCH_INFO)); > if (PatchInfoBuffer =3D=3D NULL) { > return EFI_OUT_OF_RESOURCES; > } > @@ -689,8 +694,8 @@ ShadowMicrocodePatchByFit ( > MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) > FitEntry[Index].Address; > TotalSize =3D (MicrocodeEntryPoint->DataSize =3D=3D 0) ? 2048 : > MicrocodeEntryPoint->TotalSize; > if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { > - PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEnt= ryPoint; > - PatchInfoBuffer[PatchCount].Size =3D TotalSize; > + PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntryPo= int; > + PatchInfoBuffer[PatchCount].Size =3D TotalSize; > TotalLoadSize +=3D TotalSize; > PatchCount++; > } > @@ -707,7 +712,8 @@ ShadowMicrocodePatchByFit ( > ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, > TotalLoadSize); > } >=20 > - FreePool (PatchInfoBuffer); > + CpuMpData->PatchCount =3D PatchCount; > + CpuMpData->PatchInfoBuffer =3D PatchInfoBuffer; > return EFI_SUCCESS; > } >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h > b/UefiCpuPkg/Library/MpInitLib/MpLib.h > index 7c62d75acc..51c71ad38e 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h > @@ -29,6 +29,8 @@ > #include > #include >=20 > +#include > + > #include >=20 >=20 > @@ -56,6 +58,7 @@ > // > typedef struct { > UINTN Address; > + UINTN AddressInRam; > UINTN Size; > } MICROCODE_PATCH_INFO; >=20 > @@ -273,6 +276,12 @@ struct _CPU_MP_DATA { > // driver. > // > BOOLEAN WakeUpByInitSipiSipi; > + > + // > + // Shadow infomation of the microcode patch data. > + // > + UINTN PatchCount; > + MICROCODE_PATCH_INFO *PatchInfoBuffer; > }; >=20 > extern EFI_GUID mCpuInitMpLibHobGuid; > diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > index 06e3f5d0d3..07fc05124c 100644 > --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > @@ -1,7 +1,7 @@ > /** @file > MP initialize support functions for PEI phase. >=20 > - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -291,6 +291,40 @@ CheckAndUpdateApsStatus ( > { > } >=20 > +/** > + Find the corresponding microcode patch address in ROM before the shado= w > + operation. > + > + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure= . > + @param[in] MicrocodeEntryAddr Loaded microcode address to be check= ed. > + > + @return Microcode address in ROM, or MAX_UINT64 if this microcode w= as > + not been shadowed. > +**/ > +UINT64 > +RomAddrOfShadowedMicrocode ( > + IN CPU_MP_DATA *CpuMpData, > + IN UINT64 MicrocodeEntryAddr > + ) > +{ > + UINT32 Index; > + > + if (CpuMpData->PatchInfoBuffer =3D=3D NULL) { > + // > + // No shadow. > + // > + return MicrocodeEntryAddr; > + } > + > + for (Index =3D 0; Index < CpuMpData->PatchCount; Index++) { > + if (CpuMpData->PatchInfoBuffer[Index].AddressInRam =3D=3D > MicrocodeEntryAddr) { > + return CpuMpData->PatchInfoBuffer[Index].Address; > + } > + } > + > + return MicrocodeEntryAddr; > +} > + > /** > Build the microcode patch HOB that contains the base address and size = of the > microcode patch stored in the memory. > @@ -306,8 +340,11 @@ BuildMicrocodeCacheHob ( > EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; > UINTN HobDataLength; > UINT32 Index; > + UINT64 *ProcessorSpecificPatchOffset; > + UINT64 *ProcessorSpecificPatchAddrInRom; >=20 > HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + > + sizeof (UINT64) * CpuMpData->CpuCount + > sizeof (UINT64) * CpuMpData->CpuCount; >=20 > MicrocodeHob =3D AllocatePool (HobDataLength); > @@ -317,10 +354,14 @@ BuildMicrocodeCacheHob ( > } >=20 > // > - // Store the information of the memory region that holds the microcode > patches. > + // Store information of the memory region that holds the microcode pat= ches. > // > MicrocodeHob->MicrocodePatchAddress =3D CpuMpData- > >MicrocodePatchAddress; > MicrocodeHob->MicrocodePatchRegionSize =3D CpuMpData- > >MicrocodePatchRegionSize; > + ProcessorSpecificPatchOffset =3D > + (UINT64*) ((UINTN )MicrocodeHob + sizeof > (EDKII_MICROCODE_PATCH_HOB)); > + ProcessorSpecificPatchAddrInRom =3D > + (UINT64*) ((UINTN )ProcessorSpecificPatchOffset + sizeof (UINT64) * > CpuMpData->CpuCount); >=20 > // > // Store the detected microcode patch for each processor as well. > @@ -328,10 +369,15 @@ BuildMicrocodeCacheHob ( > MicrocodeHob->ProcessorCount =3D CpuMpData->CpuCount; > for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { > if (CpuMpData->CpuData[Index].MicrocodeEntryAddr !=3D 0) { > - MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D > + ProcessorSpecificPatchOffset[Index] =3D > CpuMpData->CpuData[Index].MicrocodeEntryAddr - CpuMpData- > >MicrocodePatchAddress; > + ProcessorSpecificPatchAddrInRom[Index] =3D > RomAddrOfShadowedMicrocode ( > + CpuMpData, > + CpuMpData->CpuData[Inde= x].MicrocodeEntryAddr > + ); > } else { > - MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; > + ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; > + ProcessorSpecificPatchAddrInRom[Index] =3D MAX_UINT64; > } > } >=20 > -- > 2.19.1.windows.1