From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web09.2210.1582684413131060035 for ; Tue, 25 Feb 2020 18:33:33 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 18:33:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,486,1574150400"; d="scan'208";a="237882005" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 25 Feb 2020 18:33:32 -0800 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 18:33:31 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 18:33:31 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.5]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.196]) with mapi id 14.03.0439.000; Wed, 26 Feb 2020 10:33:28 +0800 From: "Ni, Ray" To: "Chaganty, Rangasai V" , "Fu, Siyuan" , "devel@edk2.groups.io" Subject: Re: [Patch] IntelSiliconPkg: Declare zero array explicitly to avoid compiler error. Thread-Topic: [Patch] IntelSiliconPkg: Declare zero array explicitly to avoid compiler error. Thread-Index: AQHV7EWMn14NRwNF/EqWK2FNGhLowKgswVTw Date: Wed, 26 Feb 2020 02:33:27 +0000 Deferred-Delivery: Wed, 26 Feb 2020 02:33:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C453DAB@SHSMSX104.ccr.corp.intel.com> References: <20200226010753.44716-1-siyuan.fu@intel.com> In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Chaganty, Rangasai V > Sent: Wednesday, February 26, 2020 9:39 AM > To: Fu, Siyuan ; devel@edk2.groups.io > Cc: Ni, Ray > Subject: RE: [Patch] IntelSiliconPkg: Declare zero array explicitly to av= oid compiler error. >=20 > Reviewed-by: Sai Chaganty >=20 > -----Original Message----- > From: Fu, Siyuan > Sent: Tuesday, February 25, 2020 5:08 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > Subject: [Patch] IntelSiliconPkg: Declare zero array explicitly to avoid = compiler error. >=20 > This patch fixes a potential compiler error introduced by commit b0099a39= bd since not all compiler can support empty > array member. >=20 > BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Signed-off-by: Siyuan Fu > --- > .../Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowIn= foHob.h > b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h > index d1a9d79a51..d887b39123 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob. > +++ h > @@ -33,7 +33,7 @@ typedef struct { > // An array with MicrocodeCount elements that stores > // the shadowed microcode patch address in memory. > // > - UINT64 MicrocodeAddrInMemory[]; > + UINT64 MicrocodeAddrInMemory[0]; > // > // A buffer which contains details about the storage information > // specific to StorageType. > -- > 2.19.1.windows.1 >=20