From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.5047.1582703153278750058 for ; Tue, 25 Feb 2020 23:45:53 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 23:45:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,487,1574150400"; d="scan'208";a="241583833" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga006.jf.intel.com with ESMTP; 25 Feb 2020 23:45:52 -0800 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 23:45:33 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 23:45:33 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.5]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.141]) with mapi id 14.03.0439.000; Wed, 26 Feb 2020 15:45:31 +0800 From: "Ni, Ray" To: Leo Duran , "devel@edk2.groups.io" , "Wu, Hao A" , "Fu, Siyuan" CC: "Dong, Eric" , Laszlo Ersek Subject: Re: [PATCH 2/2] UefiCpuPkg: MpInitLib: Exclude code no pertinent to AMD processors. Thread-Topic: [PATCH 2/2] UefiCpuPkg: MpInitLib: Exclude code no pertinent to AMD processors. Thread-Index: AQHV7BOC1u+fhC2LZEqC6uXIv0UQ06gtGOFg Date: Wed, 26 Feb 2020 07:45:30 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C454254@SHSMSX104.ccr.corp.intel.com> References: <1582659566-9893-1-git-send-email-leo.duran@amd.com> <1582659566-9893-3-git-send-email-leo.duran@amd.com> In-Reply-To: <1582659566-9893-3-git-send-email-leo.duran@amd.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable + Hao Wu and Siyuan Fu for review. > -----Original Message----- > From: Leo Duran > Sent: Wednesday, February 26, 2020 3:39 AM > To: devel@edk2.groups.io > Cc: Leo Duran ; Dong, Eric ; Ni, = Ray ; Laszlo Ersek > > Subject: [PATCH 2/2] UefiCpuPkg: MpInitLib: Exclude code no pertinent to = AMD processors. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2556 >=20 > This patch uses the newly exported StandardSignatureIsAuthenticAMD functi= on > from LocalApicLib, to divert code paths not pertinent to AMD processors. > Specifically, the PlatformId MSR and embedded Microcode patches are not > relevant on AMD-based platforms. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Library/MpInitLib/Microcode.c | 17 +++++++++++++++-- > UefiCpuPkg/Library/MpInitLib/MpLib.c | 11 +++++++++-- > 2 files changed, 24 insertions(+), 4 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Librar= y/MpInitLib/Microcode.c > index 1562959..750681d 100644 > --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c > +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c > @@ -2,6 +2,8 @@ > Implementation of loading microcode on processors. >=20 > Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.
> + Copyright (c) 2020, AMD Inc. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -97,9 +99,13 @@ MicrocodeDetect ( > UINT32 ThreadId; > BOOLEAN IsBspCallIn; >=20 > - if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0) { > + // > + // NOTE: Embedded Microcode patches are not relevant on AMD platforms. > + // > + if (CpuMpData->MicrocodePatchRegionSize =3D=3D 0 || > + StandardSignatureIsAuthenticAMD ()) { > // > - // There is no microcode patches > + // There are no microcode patches > // > return; > } > @@ -350,6 +356,13 @@ IsProcessorMatchedMicrocodePatch ( > UINTN Index; > CPU_AP_DATA *CpuData; >=20 > + // > + // NOTE: PlatformId or embedded Microcode patches are not relevant on = AMD platforms. > + // > + if (StandardSignatureIsAuthenticAMD ()) { > + return FALSE; > + } > + > for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { > CpuData =3D &CpuMpData->CpuData[Index]; > if ((ProcessorSignature =3D=3D CpuData->ProcessorSignature) && > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/Mp= InitLib/MpLib.c > index d0fbc17..290e7bf 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -2,6 +2,8 @@ > CPU MP Initialize Library common functions. >=20 > Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
> + Copyright (c) 2020, AMD Inc. All rights reserved.
> + > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -564,8 +566,13 @@ InitializeApData ( > CpuMpData->CpuData[ProcessorNumber].Waiting =3D FALSE; > CpuMpData->CpuData[ProcessorNumber].CpuHealthy =3D (BistData =3D=3D 0)= ? TRUE : FALSE; >=20 > - PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); > - CpuMpData->CpuData[ProcessorNumber].PlatformId =3D (UINT8) PlatformIdM= sr.Bits.PlatformId; > + // > + // NOTE: PlatformId is not relevant on AMD platforms. > + // > + if (!StandardSignatureIsAuthenticAMD ()) { > + PlatformIdMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); > + CpuMpData->CpuData[ProcessorNumber].PlatformId =3D (UINT8)PlatformId= Msr.Bits.PlatformId; > + } >=20 > AsmCpuid ( > CPUID_VERSION_INFO, > -- > 2.7.4