From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.4995.1582703860469564982 for ; Tue, 25 Feb 2020 23:57:40 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Feb 2020 23:57:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,487,1574150400"; d="scan'208";a="410519801" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga005.jf.intel.com with ESMTP; 25 Feb 2020 23:57:39 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 23:57:24 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 25 Feb 2020 23:57:24 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.5]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.225]) with mapi id 14.03.0439.000; Wed, 26 Feb 2020 15:57:22 +0800 From: "Ni, Ray" To: Laszlo Ersek , "devel@edk2.groups.io" , "leo.duran@amd.com" , "Wu, Hao A" , "Fu, Siyuan" CC: "Dong, Eric" Subject: Re: [edk2-devel] [PATCH 0/2] UefiCpuPkg/Library: Fix bug in MpInitLib Thread-Topic: [edk2-devel] [PATCH 0/2] UefiCpuPkg/Library: Fix bug in MpInitLib Thread-Index: AQHV7B0pGPIUTxhG5EqTSXQjAjWqRagsIFiAgAD60nA= Date: Wed, 26 Feb 2020 07:57:21 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C4542DA@SHSMSX104.ccr.corp.intel.com> References: <1582659566-9893-1-git-send-email-leo.duran@amd.com> In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, > > BTW, reading the PlatformId MSR was already being done by MicrocodeDete= ct(), > > but it never affected AMD-based platforms as the flow never gets that f= ar, since > > the Detect routine bails out early when it finds the size of the patch = is zero. You are saying that PlatformId MSR access is not performed by CPU in old co= de because of the zero size uCode. But now with Hao or Siyuan's change, the PlatformId MSR access is always pe= rformed even when there is no uCode. It sounds like a regression to optimiz= ation to me. Did you evaluate the path to avoid accessing PlatformID MSR when uCode does= n't exist? So that the API to detect AMD processor is not needed at all. Thanks, Ray