From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.9003.1582777349258114171 for ; Wed, 26 Feb 2020 20:22:29 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Feb 2020 20:22:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,490,1574150400"; d="scan'208";a="436900326" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 26 Feb 2020 20:22:28 -0800 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 26 Feb 2020 20:22:28 -0800 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 26 Feb 2020 20:22:27 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.206]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.145]) with mapi id 14.03.0439.000; Thu, 27 Feb 2020 12:22:25 +0800 From: "Ni, Ray" To: "Fu, Siyuan" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Gao, Liming" Subject: Re: [Patch] IntelSiliconPkg/ShadowMicrocodePei: Fix GCC build error. Thread-Topic: [Patch] IntelSiliconPkg/ShadowMicrocodePei: Fix GCC build error. Thread-Index: AQHV7RFqhTIDgMTTeUeJSgF43lJEjKgucKig Date: Thu, 27 Feb 2020 04:22:23 +0000 Deferred-Delivery: Thu, 27 Feb 2020 04:22:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C461BA4@SHSMSX104.ccr.corp.intel.com> References: <20200227015826.67948-1-siyuan.fu@intel.com> In-Reply-To: <20200227015826.67948-1-siyuan.fu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Fu, Siyuan > Sent: Thursday, February 27, 2020 9:58 AM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V ; Gao, Liming > > Subject: [Patch] IntelSiliconPkg/ShadowMicrocodePei: Fix GCC build error. >=20 > This patch fixes compiler error introduced by commit > b0099a39bd. >=20 > BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 > Cc: Ray Ni > Cc: Rangasai V Chaganty > Cc: Liming Gao > Signed-off-by: Siyuan Fu > --- > .../Feature/ShadowMicrocode/ShadowMicrocodePei.c | 2 +- > .../Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shadow= MicrocodePei.c > b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePe= i.c > index 7e4084247e..8d6574f667 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicroco= dePei.c > +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicroco= dePei.c > @@ -247,7 +247,7 @@ ShadowMicrocodePatchWorker ( > (VOID *) Patches[Index].Address, > Patches[Index].Size > ); > - MicrocodeAddressInMemory[Index] =3D (UINT64) Walker; > + MicrocodeAddressInMemory[Index] =3D (UINT64) (UINTN) Walker; > Flashcontext->MicrocodeAddressInFlash[Index] =3D (UINT64) Patches[I= ndex].Address; > Walker +=3D Patches[Index].Size; > } > diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowIn= foHob.h > b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h > index d887b39123..1daae1234a 100644 > --- a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h > +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h > @@ -58,7 +58,7 @@ typedef struct { > // microcode patch address on flash. The address is placed in same > // order as the microcode patches in MicrocodeAddrInMemory. > // > - UINT64 MicrocodeAddressInFlash[]; > + UINT64 MicrocodeAddressInFlash[0]; > } EFI_MICROCODE_STORAGE_TYPE_FLASH_CONTEXT; >=20 > #endif > -- > 2.19.1.windows.1