From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web11.4442.1587641817418737295 for ; Thu, 23 Apr 2020 04:36:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) IronPort-SDR: gomwQDhqFHLB0FFDooQI7swWVoYWfyUBth3LBnLT4V8Y6zaplV4/iJ0VgP6zbovBWF+35ZWIR5 hgeaXcXW+Y+w== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2020 04:36:56 -0700 IronPort-SDR: rfjskUSt4yJTNIhfKeqkSmH1JJyrWUxodu95bKCUx9J3kxNQp+ePkNJZddowRhBxAF6wTEoXpe Zyq+9WZgnnog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,307,1583222400"; d="scan'208";a="402891960" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga004.jf.intel.com with ESMTP; 23 Apr 2020 04:36:56 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 23 Apr 2020 04:36:47 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 23 Apr 2020 04:36:47 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Thu, 23 Apr 2020 04:36:47 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.225]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.22]) with mapi id 14.03.0439.000; Thu, 23 Apr 2020 19:36:44 +0800 From: "Ni, Ray" To: Wasim Khan , "devel@edk2.groups.io" CC: "ard.biesheuvel@linaro.org" , "v.sethi@nxp.com" , "Wu, Hao A" Subject: Re: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Checks Thread-Topic: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Checks Thread-Index: AQHWGVwbXTEaHgr5wUWbkKbOVktonKiGkeqg Date: Thu, 23 Apr 2020 11:36:44 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C50A98E@SHSMSX104.ccr.corp.intel.com> References: <1587638612-13056-1-git-send-email-wasim.khan@nxp.com> In-Reply-To: <1587638612-13056-1-git-send-email-wasim.khan@nxp.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks for fixing the check. PCI_ROOT_BRIDGE_APERTURE.Base/Limit are device address while the memory spa= ce in GCD belongs to host domain. So, host address for Mem/Pmem should be below 4GB while device address can = across 4GB. Can you enhance the check as below? ASSERT (TO_HOST_ADDRESS (Bridge->Mem.Limit, Bridge->Mem.Translation) < SI= ZE_4GB); if (TO_HOST_ADDRESS (Bridge->Mem.Limit, Bridge->Mem.Translation) >=3D SIZ= E_4GB) { return NULL; } It will look more precise and can detect invalid Mem/Pmem resource. > -----Original Message----- > From: Wasim Khan > Sent: Thursday, April 23, 2020 6:44 PM > To: devel@edk2.groups.io > Cc: ard.biesheuvel@linaro.org; v.sethi@nxp.com; Wu, Hao A ; Ni, Ray ; Wasim > Khan > Subject: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Ch= ecks >=20 > With Address Translation Support, it is possible and > also correct that Mem and Pmem Limit cross the 4GB boundary. > Update the checks so that Mem/PMem Limit should not cross 4GB > from the Mem/PMem Base address. >=20 > Signed-off-by: Wasim Khan > --- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > index d304fae..9cf7e98 100644 > --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c > @@ -117,8 +117,8 @@ CreateRootBridge ( > // Make sure Mem and MemAbove4G apertures are valid > // > if (RESOURCE_VALID (&Bridge->Mem)) { > - ASSERT (Bridge->Mem.Limit < SIZE_4GB); > - if (Bridge->Mem.Limit >=3D SIZE_4GB) { > + ASSERT (Bridge->Mem.Limit < (Bridge->Mem.Base + SIZE_4GB)); > + if (Bridge->Mem.Limit >=3D (Bridge->Mem.Base + SIZE_4GB)) { > return NULL; > } > } > @@ -129,8 +129,8 @@ CreateRootBridge ( > } > } > if (RESOURCE_VALID (&Bridge->PMem)) { > - ASSERT (Bridge->PMem.Limit < SIZE_4GB); > - if (Bridge->PMem.Limit >=3D SIZE_4GB) { > + ASSERT (Bridge->PMem.Limit < (Bridge->PMem.Base + SIZE_4GB)); > + if (Bridge->PMem.Limit >=3D (Bridge->PMem.Base + SIZE_4GB)) { > return NULL; > } > } > -- > 2.7.4