From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.6776.1588926392895836529 for ; Fri, 08 May 2020 01:26:33 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: ray.ni@intel.com) IronPort-SDR: 7aMPTBlSnJJfMczAFl1hcczfdYRR88DHacZkasouyUi6/SgfkvdaRnkVTXqj7fifxsJaVsbk2U I1jODg6QLM/w== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2020 01:26:32 -0700 IronPort-SDR: 8RvHbP78UwwdB8p1O3/Xbsf94uLfRXEnrMNcebWfrPrVFsJRIvNC+q1Ceh3dnFC+isSi1MPJN5 aE4Ixm8ICApQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,366,1583222400"; d="scan'208";a="249563477" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga007.jf.intel.com with ESMTP; 08 May 2020 01:26:31 -0700 Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 8 May 2020 01:26:30 -0700 Received: from fmsmsx607.amr.corp.intel.com (10.18.126.87) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 8 May 2020 01:26:30 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by fmsmsx607.amr.corp.intel.com (10.18.126.87) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Fri, 8 May 2020 01:26:29 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.92]) with mapi id 14.03.0439.000; Fri, 8 May 2020 16:26:26 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Thread-Topic: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Thread-Index: AQHVmdJK3T9Y1rxzHkawV8SqYkiDX6e92zmAgAFQkwCAAfiR8IB5l2IAgBB2hwCAAMscYIAAodCAgAEMp7CANMfpAIABF56AgAAFRgCAALaU0A== Date: Fri, 8 May 2020 08:26:26 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C52FD2F@SHSMSX104.ccr.corp.intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> <15D3127B934F51D3.12315@groups.io> <95C5C2B113DE604FB208120C742E9824579171C4@BGSMSX101.gar.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C3A05B7@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E98245797C292@BGSMSX101.gar.corp.intel.com> <15E1AFB3EABD031C.30484@groups.io> <734D49CCEBEEF84792F5B80ED585239D5C47E0CF@SHSMSX104.ccr.corp.intel.com> <95C5C2B113DE604FB208120C742E9824579C6B6A@BGSMSX101.gar.corp.intel.com> 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