From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.6569.1589174693655083872 for ; Sun, 10 May 2020 22:24:53 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: ray.ni@intel.com) IronPort-SDR: 32/MpE9Ir6RD6whCvrlf4zUICI9B9/Srd8qtG8URtCBDdJo+TnCKPX9b7VaeeBGviOmA2LTm40 r2Hyyu5DbOug== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2020 22:24:53 -0700 IronPort-SDR: wErtas8OvPapcHWMzLWWCEpRcrqz4sQox9wg3vXUoNXNnfwPY2onpOjSgNhtoRKT/RJBrVflkx jDyBzRfq0pBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,378,1583222400"; d="scan'208,217";a="463059350" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga005.fm.intel.com with ESMTP; 10 May 2020 22:24:53 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 10 May 2020 22:24:53 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx101.amr.corp.intel.com (10.18.124.199) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 10 May 2020 22:24:52 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.77]) with mapi id 14.03.0439.000; Mon, 11 May 2020 13:24:48 +0800 From: "Ni, Ray" To: "devel@edk2.groups.io" , "afish@apple.com" , "thomas.lendacky@amd.com" CC: "Justen, Jordan L" , Laszlo Ersek , Ard Biesheuvel , "Kinney, Michael D" , "Gao, Liming" , "Dong, Eric" , Brijesh Singh , "You, Benjamin" , "Bi, Dandan" , "Dong, Guo" , "Wu, Hao A" , "Wang, Jian J" , "Ma, Maurice" Subject: Re: [edk2-devel] [PATCH v7 00/43] SEV-ES guest support Thread-Topic: [edk2-devel] [PATCH v7 00/43] SEV-ES guest support Thread-Index: AQHWGM1mq8koDOU5MUKpx39ysuf17qieIp6AgAE+bzCAAAT9AIAATReAgAK3hzA= Date: Mon, 11 May 2020 05:24:48 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C535775@SHSMSX104.ccr.corp.intel.com> References: <4da69262-e6a8-1374-2853-dab2a8f193d3@amd.com> <734D49CCEBEEF84792F5B80ED585239D5C530D55@SHSMSX104.ccr.corp.intel.com> In-Reply-To: Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_734D49CCEBEEF84792F5B80ED585239D5C535775SHSMSX104ccrcor_" --_000_734D49CCEBEEF84792F5B80ED585239D5C535775SHSMSX104ccrcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Tom, I agree with the first issue. I am not quite clear on the second one. SourceLevelDebugPkg provides source level debugging support early in SEC through SourceLevelDebugPkg\Library\DebugAgent\SecPeiDebugAgent\. It hooks all Intel SDM defined exceptions. It hooks INT32 additionally to = support breaking from HOST. It doesn't use CpuExceptionLib because it hooks in very early SEC phase. Can you use the same way? Thanks, Ray From: devel@edk2.groups.io On Behalf Of Andrew Fish= via groups.io Sent: Sunday, May 10, 2020 3:10 AM To: devel@edk2.groups.io; thomas.lendacky@amd.com Cc: Ni, Ray ; Justen, Jordan L ; Laszlo Ersek ; Ard Biesheuvel ; Kinney, Michael D ; Gao, Liming ; Dong, Eric ; Brijesh Singh ; You, Benjamin ; Bi, Dandan ; Dong, Guo ; Wu, Hao A = ; Wang, Jian J ; Ma, Maurice Subject: Re: [edk2-devel] [PATCH v7 00/43] SEV-ES guest support On May 9, 2020, at 7:34 AM, Lendacky, Thomas > wrote: On 5/9/20 1:44 AM, Ni, Ray wrote: Tom, Hi Ray, I have a bit concern on your change that directly modifies CpuExceptionHan= dlerLib to handle exception #29. Today's CpuExceptionHandlerLib simplify dumps the exception= context for every exception. Any component which wants to do specific handling of cert= ain exceptions should call RegisterCpuInterruptHandler(). Such as code in CpuDxe driver: if (HEAP_GUARD_NONSTOP_MODE || NULL_DETECTION_NONSTOP_MODE) { RegisterCpuInterruptHandler (EXCEPT_IA32_DEBUG, DebugExceptionHandler)= ; RegisterCpuInterruptHandler (EXCEPT_IA32_PAGE_FAULT, PageFaultExceptio= nHandler); } Is it possible for your feature to follow the same pattern? There are two problems: The first is that RegisterCpuInterruptHandler() is not implemented for bot= h the SEC and PEI phases, so it is not currently possible to register a han= dler that early. The second is that I need to be able to propagate an exception request fro= m the hypervisor. With the current implementation there doesn't appear to b= e an easy way to perform this propagation. If there's a way to accomplish both of the above I wouldn't be opposed to = using RegisterCpuInterruptHandler() as long as there are no #VCs that can o= ccur between initializing exception handling and and registering the #VC ha= ndler. Thomas, As you point out it is tricky dealing with XIP code. You can't have global= s that you can write and generally you use a PEI service to look tings up, = the most common thing being using a HOB. But SEC has no services and I'm no= t sure you really want to be calling into the PEI Core on a random excepti= on. Here are the best options that popped into my head after reading your emai= l 1) IDT in RAM If your code populates the IDT the IDTR gives you access to the address of= the IDTR via an instruction. The PI Spec reserves IDT - sizeof (UNITN) for= a cached copy of the PEI Services Table, but otther than that you are good= to go. It should be possible to have a global so you can have the table re= quired to implement RegisterCpuInterruptHandler(). There might be some usag= e of IDT - ( 2* sizeof(UINTN)), I know I'm guilty, so storing data after t= he IDT would be a good option. In general if your code allocates the memory= for the IDT then you can treat the IDT as part of your private context dat= a structure and that gives you access 2) IDT in ROM. For this it seems like you need a library to link in to the CpuExceptionHa= ndlerLib that allows you to override the handler. If CpuInterruptHandlerOve= rride() returns NULL you do the current behavior if not NULL then you call = the returned handler. EFI_CPU_INTERRUPT_HANDLER EFIAPI OverrideCpuInterruptHandler ( IN EFI_EXCEPTION_TYPE InterruptType ); Thanks, Andrew Fish PS Off topic, but it would also be useful to have a library that overrides= the state dump display. For example using Xcode you can always display a s= tack frame from the exception handler. Thanks, Tom Thanks, Ray -----Original Message----- From: Tom Lendacky > Sent: Saturday, May 9, 2020 3:16 AM To: devel@edk2.groups.io Cc: Justen, Jordan L >; Laszlo Ersek >; Ard B= iesheuvel >; Kinney, Mic= hael D >; Gao= , Liming >; Dong, Eric >; Ni, Ray >; Brijesh Singh >; You, Benjamin >; Bi, Dandan >; Dong, Guo >; Wu, Hao A >; Wang, Jian J >; Ma, Maurice > Subject: Re: [PATCH v7 00/43] SEV-ES guest support I was able to use the pull request method that Laszlo documented and fixed up all of the issues identified by the VS compiler. An additional change I'm planning to make for the next version (v8) of the patches is to create a NULL library instance of the VmgExitLib that will also include the #VC handler function. This will reduce the amount of code associated with this feature for platforms that don't use/support SEV-ES. Laszlo, this will mean that I will introduce a version of the VmgExitLib under OvmfPkg that will provide the majority of the functionality that is present today in UefiCpuPkg. In essence, the functionality in v7 patches 8 and 11 - 25 will now live under OvmfPkg instead of UefiCpuPkg. I think this is the better way to do this. Let me know if you have any concerns. Thanks, Tom On 4/22/20 12:41 PM, Tom Lendacky wrote: This patch series provides support for running EDK2/OVMF under SEV-ES. Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the SEV support to protect the guest register state from the hypervisor. See "AMD64 Architecture Programmer's Manual Volume 2: System Programming", section "15.35 Encrypted State (SEV-ES)" [1]. In order to allow a hypervisor to perform functions on behalf of a guest, there is architectural support for notifying a guest's operating system when certain types of VMEXITs are about to occur. This allows the guest to selectively share information with the hypervisor to satisfy the requested function. The notification is performed using a new exception, the VMM Communication exception (#VC). The information is shared through the Guest-Hypervisor Communication Block (GHCB) using the VMGEXIT instruction. The GHCB format and the protocol for using it is documented in "SEV-ES Guest-Hypervisor Communication Block Standardization" [2]. The main areas of the EDK2 code that are updated to support SEV-ES are around the exception handling support and the AP boot support. Exception support is required starting in Sec, continuing through Pei and into Dxe in order to handle #VC exceptions that are generated. Each AP requires it's own GHCB page as well as a page to hold values specific to that AP. AP booting poses some interesting challenges. The INIT-SIPI-SIPI sequence is typically used to boot the APs. However, the hypervisor is not allowed to update the guest registers. The GHCB document [2] talks about how SMP booting under SEV-ES is performed. Since the GHCB page must be a shared (unencrypted) page, the processor must be running in long mode in order for the guest and hypervisor to communicate with each other. As a result, SEV-ES is only supported under the X64 architecture. [1] https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fww= w.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F24593.pdf&data=3D02%7C01%7Cthom= as.lendacky%40amd.com%7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884e60= 8e11a82d994e183d%7C0%7C0%7C637246036118033165&sdata=3DH74fQl1n2sXzCMSoG= m1tGOKc5epMtVkGJFCidwLMl5c%3D&reserved=3D0 [2] https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fde= veloper.amd.com%2Fwp-content%2Fresources%2F56421.pdf&data=3D02%7C01%7Ct= homas.lendacky%40amd.com%7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884= e608e11a82d994e183d%7C0%7C0%7C637246036118033165&sdata=3DEwW9575nJMaWxi= zo2XrLHjrbUMJIB0WFTDLjwy%2BM%2F4k%3D&reserved=3D0 --- These patches are based on commit: be7295b36405 (".python/SpellCheck: Increase SpellCheck plugin max failures= ") Proper execution of SEV-ES relies on Bugzilla 2340 being fixed. A version of the tree (with an extra patch to workaround Bugzilla 2340) ca= n be found at: https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgithub= .com%2FAMDESE%2Fovmf%2Ftree%2Fsev-es-v14&data=3D02%7C01%7Cthomas.lendac= ky%40amd.com%7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884e608e11a82d9= 94e183d%7C0%7C0%7C637246036118033165&sdata=3DU8fIzb%2F4A8WBaiVbScxUuGDw= 22kyxxnRP5olSyTedvE%3D&reserved=3D0 Cc: Ard Biesheuvel > Cc: Benjamin You > Cc: Dandan Bi > Cc: Eric Dong > Cc: Guo Dong > Cc: Hao A Wu > Cc: Jian J Wang > Cc: Jordan Justen > Cc: Laszlo Ersek > Cc: Liming Gao > Cc: Maurice Ma > Cc: Michael D Kinney > Cc: Ray Ni > Changes since v6: - Add function comments to all functions, including local functions - Add function parameter direction to all functions (in/out) - Add support for MMIO MOVZX/MOVSX instructions - Ensure the per-CPU variable page remains encrypted - Coding-style fixes as identified by Ecc Changes since v5: - Remove extraneous VmgExitLib usage - Miscellaneous changes to address feedback (coding style, etc.) Changes since v4: - Move the SEV-ES protocol negotiation out of the SEC exception handler and into the SecMain.c file. As a result: - Move the SecGhcb related PCDs out of UefiCpuPkg and into OvmfPkg - Combine SecAMDSevVcHandler.c and PeiDxeAMDSevVcHandler.c into a single AMDSevVcHandler.c - Consolidate VmgExitLib usage into common LibraryClasses sections - Add documentation comments to the VmgExitLib functions Changes since v3: - Remove the need for the MP library finalization routine. The AP jump table address will be held by the hypervisor rather than communicated via the GHCB MSR. This removes some fragility around the UEFI to OS transition. - Rename the SEV-ES RIP reset area to SEV-ES workarea and use it to communicate the SEV-ES status, so that SEC CPU exception handling is only established for an SEV-ES guest. - Fix SMM build breakageAdd around QemuFlashPtrWrite(). - Fix SMM build breakage by adding VC exception support the SMM CPU exception handling. - Add memory fencing around the invocation of AsmVmgExit(). - Clarify comments around the SEV-ES AP reset RIP values and usage. - Move some PCD definitions from MdeModulePkg to UefiCpuPkg. - Remove the 16-bit code selector definition from MdeModulePkg Changes since v2: - Added a way to locate the SEV-ES fixed AP RIP address for starting AP's to avoid updating the actual flash image (build time location that is identified with a GUID value). - Create a VmgExit library to replace static inline functions. - Move some PCDs to the appropriate packages - Add support for writing to QEMU flash under SEV-ES - Add additional MMIO opcode support - Cleaned up the GHCB MSR CPUID protocol support Changes since v1: - Patches reworked to be more specific to the component/area being updated and order of definition/usage - Created a library for VMGEXIT-related functions to replace use of inline functions - Allocation method for GDT changed from AllocatePool to AllocatePages - Early caching only enabled for SEV-ES guests - Ensure AP loop mode set to halt loop mode for SEV-ES guests - Reserved SEC GHCB-related memory areas when S3 is enabled Tom Lendacky (43): MdeModulePkg: Create PCDs to be used in support of SEV-ES UefiCpuPkg: Create PCD to be used in support of SEV-ES MdePkg: Add the MSR definition for the GHCB register MdePkg: Add a structure definition for the GHCB MdeModulePkg/DxeIplPeim: Support GHCB pages when creating page tables MdePkg/BaseLib: Add support for the XGETBV instruction MdePkg/BaseLib: Add support for the VMGEXIT instruction UefiCpuPkg: Implement library support for VMGEXIT OvmfPkg: Prepare OvmfPkg to use the VmgExitLib library UefiPayloadPkg: Prepare UefiPayloadPkg to use the VmgExitLib library UefiCpuPkg/CpuExceptionHandler: Add base support for the #VC exception UefiCpuPkg/CpuExceptionHandler: Add support for IOIO_PROT NAE events UefiCpuPkg/CpuExceptionHandler: Support string IO for IOIO_PROT NAE events UefiCpuPkg/CpuExceptionHandler: Add support for CPUID NAE events UefiCpuPkg/CpuExceptionHandler: Add support for MSR_PROT NAE events UefiCpuPkg/CpuExceptionHandler: Add support for NPF NAE events (MMIO) UefiCpuPkg/CpuExceptionHandler: Add support for WBINVD NAE events UefiCpuPkg/CpuExceptionHandler: Add support for RDTSC NAE events UefiCpuPkg/CpuExceptionHandler: Add support for RDPMC NAE events UefiCpuPkg/CpuExceptionHandler: Add support for INVD NAE events UefiCpuPkg/CpuExceptionHandler: Add support for VMMCALL NAE events UefiCpuPkg/CpuExceptionHandler: Add support for RDTSCP NAE events UefiCpuPkg/CpuExceptionHandler: Add support for MONITOR/MONITORX NAE events UefiCpuPkg/CpuExceptionHandler: Add support for MWAIT/MWAITX NAE events UefiCpuPkg/CpuExceptionHandler: Add support for DR7 Read/Write NAE events OvmfPkg/MemEncryptSevLib: Add an SEV-ES guest indicator function OvmfPkg: Add support to perform SEV-ES initialization OvmfPkg: Create a GHCB page for use during Sec phase OvmfPkg/PlatformPei: Reserve GHCB-related areas if S3 is supported OvmfPkg: Create GHCB pages for use during Pei and Dxe phase OvmfPkg/PlatformPei: Move early GDT into ram when SEV-ES is enabled UefiCpuPkg: Create an SEV-ES workarea PCD OvmfPkg: Reserve a page in memory for the SEV-ES usage OvmfPkg/ResetVector: Add support for a 32-bit SEV check OvmfPkg/Sec: Add #VC exception handling for Sec phase OvmfPkg/Sec: Enable cache early to speed up booting OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash detection with SEV-ES is enabled UefiCpuPkg: Add a 16-bit protected mode code segment descriptor UefiCpuPkg/MpInitLib: Add CPU MP data flag to indicate if SEV-ES is enabled UefiCpuPkg: Allow AP booting under SEV-ES OvmfPkg: Use the SEV-ES work area for the SEV-ES AP reset vector OvmfPkg: Move the GHCB allocations into reserved memory UefiCpuPkg/MpInitLib: Prepare SEV-ES guest APs for OS use MdeModulePkg/MdeModulePkg.dec | 9 + OvmfPkg/OvmfPkg.dec | 9 + UefiCpuPkg/UefiCpuPkg.dec | 17 + OvmfPkg/OvmfPkgIa32.dsc | 6 + OvmfPkg/OvmfPkgIa32X64.dsc | 6 + OvmfPkg/OvmfPkgX64.dsc | 6 + OvmfPkg/OvmfXen.dsc | 1 + UefiCpuPkg/UefiCpuPkg.dsc | 2 + UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 2 + UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 2 + OvmfPkg/OvmfPkgX64.fdf | 9 + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 + MdePkg/Library/BaseLib/BaseLib.inf | 4 + OvmfPkg/PlatformPei/PlatformPei.inf | 7 + .../FvbServicesRuntimeDxe.inf | 2 + OvmfPkg/ResetVector/ResetVector.inf | 8 + OvmfPkg/Sec/SecMain.inf | 4 + .../DxeCpuExceptionHandlerLib.inf | 5 + .../PeiCpuExceptionHandlerLib.inf | 5 + .../SecPeiCpuExceptionHandlerLib.inf | 5 + .../SmmCpuExceptionHandlerLib.inf | 5 + UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 4 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 + UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf | 33 + .../Core/DxeIplPeim/X64/VirtualMemory.h | 12 +- MdePkg/Include/Library/BaseLib.h | 31 + MdePkg/Include/Register/Amd/Fam17Msr.h | 42 + MdePkg/Include/Register/Amd/Ghcb.h | 136 ++ OvmfPkg/Include/Library/MemEncryptSevLib.h | 12 + .../QemuFlash.h | 13 + UefiCpuPkg/CpuDxe/CpuGdt.h | 4 +- UefiCpuPkg/Include/Library/VmgExitLib.h | 117 ++ .../CpuExceptionHandlerLib/AMDSevVcCommon.h | 49 + .../CpuExceptionCommon.h | 2 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 68 +- .../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +- .../Core/DxeIplPeim/X64/DxeLoadFunc.c | 11 +- .../Core/DxeIplPeim/X64/VirtualMemory.c | 57 +- MdePkg/Library/BaseLib/Ia32/GccInline.c | 45 + MdePkg/Library/BaseLib/X64/GccInline.c | 47 + .../MemEncryptSevLibInternal.c | 75 +- OvmfPkg/PlatformPei/AmdSev.c | 89 + OvmfPkg/PlatformPei/MemDetect.c | 23 + .../QemuFlash.c | 23 +- .../QemuFlashDxe.c | 22 + .../QemuFlashSmm.c | 16 + OvmfPkg/Sec/SecMain.c | 188 +- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 +- .../CpuExceptionHandlerLib/AMDSevVcHandler.c | 40 + .../CpuExceptionCommon.c | 2 +- .../Ia32/ArchAMDSevVcHandler.c | 38 + .../PeiDxeSmmCpuException.c | 16 + .../SecPeiCpuException.c | 16 + .../X64/ArchAMDSevVcHandler.c | 1699 +++++++++++++++++ UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 113 +- UefiCpuPkg/Library/MpInitLib/MpLib.c | 265 ++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 19 + UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c | 293 +++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +- MdeModulePkg/MdeModulePkg.uni | 8 + MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 37 + MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 + MdePkg/Library/BaseLib/X64/VmgExit.nasm | 32 + MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 + OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 100 + OvmfPkg/ResetVector/Ia32/PageTables64.asm | 350 +++- OvmfPkg/ResetVector/ResetVector.nasmb | 20 + .../X64/ExceptionHandlerAsm.nasm | 17 + UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 2 +- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 15 + UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 4 +- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 370 +++- UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni | 15 + .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 + UefiCpuPkg/UefiCpuPkg.uni | 11 + 75 files changed, 4707 insertions(+), 102 deletions(-) create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCom= mon.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcHan= dler.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchAM= DSevVcHandler.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMD= SevVcHandler.c create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm create mode 100644 OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni --_000_734D49CCEBEEF84792F5B80ED585239D5C535775SHSMSX104ccrcor_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Tom,

I agree with the first issue. I am not quite clear = on the second one.

 

SourceLevelDebugPkg provides source level debugging= support early in SEC
through SourceLevelDebugPkg\Library\DebugAgent\SecPeiDebugAgent\.

 

It hooks all Intel SDM defined exceptions. It hooks= INT32 additionally to support breaking from HOST.

It doesn’t use CpuExceptionLib because it hoo= ks in very early SEC phase.

 

Can you use the same way?

 

Thanks,
Ray

 

From: devel@edk2.groups.io <devel@edk2.gr= oups.io> On Behalf Of Andrew Fish via groups.io
Sent: Sunday, May 10, 2020 3:10 AM
To: devel@edk2.groups.io; thomas.lendacky@amd.com
Cc: Ni, Ray <ray.ni@intel.com>; Justen, Jordan L <jordan.l= .justen@intel.com>; Laszlo Ersek <lersek@redhat.com>; Ard Biesheuv= el <ard.biesheuvel@linaro.org>; Kinney, Michael D <michael.d.kinne= y@intel.com>; Gao, Liming <liming.gao@intel.com>; Dong, Eric <eric.dong@intel.com>; Brijesh Singh <brijesh.singh@amd.com>;= You, Benjamin <benjamin.you@intel.com>; Bi, Dandan <dandan.bi@int= el.com>; Dong, Guo <guo.dong@intel.com>; Wu, Hao A <hao.a.wu@in= tel.com>; Wang, Jian J <jian.j.wang@intel.com>; Ma, Maurice <ma= urice.ma@intel.com>
Subject: Re: [edk2-devel] [PATCH v7 00/43] SEV-ES guest support

 

 



On May 9, 2020, at 7:34 AM, Lendacky, Thomas <thomas.lendacky@amd.com> wr= ote:

 

On 5/9/20 1:44 AM, Ni, Ray wrote:

Tom,


Hi Ray,


I have a bit concern on your change that directly= modifies CpuExceptionHandlerLib to handle
exception #29. Today's CpuExceptionHandlerLib simplify dumps the exception= context for
every exception. Any component which wants to do specific handling of cert= ain exceptions
should call RegisterCpuInterruptHandler(). Such as code in CpuDxe driver:<= br>   if (HEAP_GUARD_NONSTOP_MODE || NULL_DETECTION_NONSTOP_MODE) {<= br>     RegisterCpuInterruptHandler (EXCEPT_IA32_DEBUG, De= bugExceptionHandler);
    RegisterCpuInterruptHandler (EXCEPT_IA32_PAGE_FAUL= T, PageFaultExceptionHandler);
  }
Is it possible for your feature to follow the same pattern?


There are two problems:

The first is that RegisterCpuInterruptHandler() is not implemented for bot= h the SEC and PEI phases, so it is not currently possible to register a han= dler that early.

The second is that I need to be able to propagate an exception request fro= m the hypervisor. With the current implementation there doesn't appear to b= e an easy way to perform this propagation.

If there's a way to accomplish both of the above I wouldn't be opposed to = using RegisterCpuInterruptHandler() as long as there are no #VCs that can o= ccur between initializing exception handling and and registering the #VC ha= ndler.

 

Thomas,

 

As you point out it is tricky dealing with XIP code= . You can't have globals that you can write and generally you use a PEI ser= vice to look tings up, the most common thing being using a HOB. But SEC has= no services and I'm not sure you really want to be calling into the PEI Core on a random  exception. 

 

Here are the best options that popped into my head = after reading your email

1) IDT in RAM

If your code populates the IDT the IDTR gives you a= ccess to the address of the IDTR via an instruction. The PI Spec reserves I= DT - sizeof (UNITN) for a cached copy of the PEI Services Table, but otther= than that you are good to go. It should be possible to have a global so you can have the table required to implem= ent RegisterCpuInterruptHandler(). There might be some usage  of IDT -= ( 2* sizeof(UINTN)), I know I'm guilty, so storing data after the IDT woul= d be a good option. In general if your code allocates the memory for the IDT then you can treat the IDT as part = of your private context data structure and that gives you access =

 

2) IDT in ROM. 

For this it seems like you need a library to link i= n to the CpuExceptionHandlerLib that allows you to override the handle= r. If CpuInterruptHandlerOverride() returns NULL you do the current behavio= r if not NULL then you call the returned handler. 

 

EFI_CPU_INTERRUPT_HANDLER

EFIAPI

OverrideCpuInterruptHandler (

  IN EFI_EXCEPTION_TYPE     &nb= sp;      InterruptType

  );

 

Thanks,

 

Andrew Fish

 

PS Off topic, but it would also be useful to have a= library that overrides the state dump display. For example using Xcode you= can always display a stack frame from the exception handler. 

 



Thanks,
Tom


Thanks,
Ray

-----Original Message-----
From: Tom Lendacky <<= span style=3D"font-size:9.0pt;font-family:"Helvetica",sans-serif"= >thomas.lendacky@amd.com>
Sent: Saturday, May 9, 2020 3:16 AM
To: devel@edk2.groups.io<= /span>
Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Laszlo Ersek <lersek@redhat.com>; Ard Biesheuvel
<ard.biesheuvel@l= inaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.g= ao@intel.com>; Dong,
Eric <eric.dong@intel.c= om>; Ni, Ray <ray.ni@intel.com>; Brijesh Singh <brije= sh.singh@amd.com>; You, Benjamin
<benjamin.you@intel.= com>; Bi, Dandan <dandan.bi@intel.com>; Dong, Guo <guo.dong@int= el.com>; Wu, Hao A
<hao.a.wu@intel.com>; Wang, Jian J <jian.j.wang@intel.com>; Ma, Maurice <maurice.= ma@intel.com>
Subject: Re: [PATCH v7 00/43] SEV-ES guest support

I was able to use the pull request method that Laszlo documented and fixed=
up all of the issues identified by the VS compiler.

An additional change I'm planning to make for the next version (v8) of the=
patches is to create a NULL library instance of the VmgExitLib that will also include the #VC handler function. This will reduce the amount of code=
associated with this feature for platforms that don't use/support SEV-ES.<= br>
Laszlo, this will mean that I will introduce a version of the VmgExitLib under OvmfPkg that will provide the majority of the functionality that is<= br> present today in UefiCpuPkg. In essence, the functionality in v7 patches 8=
and 11 - 25 will now live under OvmfPkg instead of UefiCpuPkg. I think
this is the better way to do this. Let me know if you have any concerns.
Thanks,
Tom

On 4/22/20 12:41 PM, Tom Lendacky wrote:

This patch series = provides support for running EDK2/OVMF under SEV-ES.

Secure Encrypted Virtualization - Encrypted State (SEV-ES) expands on the<= br> SEV support to protect the guest register state from the hypervisor. See "AMD64 Architecture Programmer's Manual Volume 2: System Programming&= quot;,
section "15.35 Encrypted State (SEV-ES)" [1].

In order to allow a hypervisor to perform functions on behalf of a guest,<= br> there is architectural support for notifying a guest's operating system when certain types of VMEXITs are about to occur. This allows the guest to=
selectively share information with the hypervisor to satisfy the requested=
function. The notification is performed using a new exception, the VMM
Communication exception (#VC). The information is shared through the
Guest-Hypervisor Communication Block (GHCB) using the VMGEXIT instruction.=
The GHCB format and the protocol for using it is documented in "SEV-E= S
Guest-Hypervisor Communication Block Standardization" [2].

The main areas of the EDK2 code that are updated to support SEV-ES are
around the exception handling support and the AP boot support.

Exception support is required starting in Sec, continuing through Pei
and into Dxe in order to handle #VC exceptions that are generated.  E= ach
AP requires it's own GHCB page as well as a page to hold values specific to that AP.

AP booting poses some interesting challenges. The INIT-SIPI-SIPI sequence<= br> is typically used to boot the APs. However, the hypervisor is not allowed<= br> to update the guest registers. The GHCB document [2] talks about how SMP booting under SEV-ES is performed.

Since the GHCB page must be a shared (unencrypted) page, the processor
must be running in long mode in order for the guest and hypervisor to
communicate with each other. As a result, SEV-ES is only supported under the X64 architecture.

[1] https://nam11.safeli= nks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fwww.amd.com%2Fsystem%2Ffile= s%2FTechDocs%2F24593.pdf&amp;data=3D02%7C01%7Cthomas.lendacky%40amd.com= %7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884e608e11a82d994e183d%7C0%= 7C0%7C637246036118033165&amp;sdata=3DH74fQl1n2sXzCMSoGm1tGOKc5epMtVkGJF= CidwLMl5c%3D&amp;reserved=3D0
[2] https://nam11= .safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fdeveloper.amd.com%2F= wp-content%2Fresources%2F56421.pdf&amp;data=3D02%7C01%7Cthomas.lendacky= %40amd.com%7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884e608e11a82d994= e183d%7C0%7C0%7C637246036118033165&amp;sdata=3DEwW9575nJMaWxizo2XrLHjrb= UMJIB0WFTDLjwy%2BM%2F4k%3D&amp;reserved=3D0

---

These patches are based on commit:
be7295b36405 (".python/SpellCheck: Increase SpellCheck plugin max fai= lures")

Proper execution of SEV-ES relies on Bugzilla 2340 being fixed.

A version of the tree (with an extra patch to workaround Bugzilla 2340) ca= n
be found at:
ht= tps://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgithub.co= m%2FAMDESE%2Fovmf%2Ftree%2Fsev-es-v14&amp;data=3D02%7C01%7Cthomas.lenda= cky%40amd.com%7Cf5d7875dfcf54e45c42208d7f3e4676b%7C3dd8961fe4884e608e11a82d= 994e183d%7C0%7C0%7C637246036118033165&amp;sdata=3DU8fIzb%2F4A8WBaiVbScx= UuGDw22kyxxnRP5olSyTedvE%3D&amp;reserved=3D0

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Benjamin You <be= njamin.you@intel.com>
Cc: Dandan Bi <dandan.b= i@intel.com>
Cc: Eric Dong <eric.don= g@intel.com>
Cc: Guo Dong <guo.dong= @intel.com>
Cc: Hao A Wu <hao.a.wu= @intel.com>
Cc: Jian J Wang <jian= .j.wang@intel.com>
Cc: Jordan Justen <= jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@= redhat.com>
Cc: Liming Gao <liming= .gao@intel.com>
Cc: Maurice Ma <mauric= e.ma@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ray Ni <ray.ni@intel.c= om>

Changes since v6:
- Add function comments to all functions, including local functions
- Add function parameter direction to all functions (in/out)
- Add support for MMIO MOVZX/MOVSX instructions
- Ensure the per-CPU variable page remains encrypted
- Coding-style fixes as identified by Ecc

Changes since v5:
- Remove extraneous VmgExitLib usage
- Miscellaneous changes to address feedback (coding style, etc.)

Changes since v4:
- Move the SEV-ES protocol negotiation out of the SEC exception handler    and into the SecMain.c file. As a result:
   - Move the SecGhcb related PCDs out of UefiCpuPkg and in= to OvmfPkg
   - Combine SecAMDSevVcHandler.c and PeiDxeAMDSevVcHandler= .c into a
     single AMDSevVcHandler.c
- Consolidate VmgExitLib usage into common LibraryClasses sections
- Add documentation comments to the VmgExitLib functions

Changes since v3:
- Remove the need for the MP library finalization routine. The AP
   jump table address will be held by the hypervisor rather= than
   communicated via the GHCB MSR. This removes some fragili= ty around
   the UEFI to OS transition.
- Rename the SEV-ES RIP reset area to SEV-ES workarea and use it to
   communicate the SEV-ES status, so that SEC CPU exception= handling is
   only established for an SEV-ES guest.
- Fix SMM build breakageAdd around QemuFlashPtrWrite().
- Fix SMM build breakage by adding VC exception support the SMM CPU
   exception handling.
- Add memory fencing around the invocation of AsmVmgExit().
- Clarify comments around the SEV-ES AP reset RIP values and usage.
- Move some PCD definitions from MdeModulePkg to UefiCpuPkg.
- Remove the 16-bit code selector definition from MdeModulePkg

Changes since v2:
- Added a way to locate the SEV-ES fixed AP RIP address for starting
   AP's to avoid updating the actual flash image (build tim= e location
   that is identified with a GUID value).
- Create a VmgExit library to replace static inline functions.
- Move some PCDs to the appropriate packages
- Add support for writing to QEMU flash under SEV-ES
- Add additional MMIO opcode support
- Cleaned up the GHCB MSR CPUID protocol support

Changes since v1:
- Patches reworked to be more specific to the component/area being updated=
   and order of definition/usage
- Created a library for VMGEXIT-related functions to replace use of inline=
   functions
- Allocation method for GDT changed from AllocatePool to AllocatePages
- Early caching only enabled for SEV-ES guests
- Ensure AP loop mode set to halt loop mode for SEV-ES guests
- Reserved SEC GHCB-related memory areas when S3 is enabled

Tom Lendacky (43):
   MdeModulePkg: Create PCDs to be used in support of SEV-E= S
   UefiCpuPkg: Create PCD to be used in support of SEV-ES    MdePkg: Add the MSR definition for the GHCB register
   MdePkg: Add a structure definition for the GHCB
   MdeModulePkg/DxeIplPeim: Support GHCB pages when creatin= g page tables
   MdePkg/BaseLib: Add support for the XGETBV instruction    MdePkg/BaseLib: Add support for the VMGEXIT instruction<= br>    UefiCpuPkg: Implement library support for VMGEXIT
   OvmfPkg: Prepare OvmfPkg to use the VmgExitLib library    UefiPayloadPkg: Prepare UefiPayloadPkg to use the VmgExi= tLib library
   UefiCpuPkg/CpuExceptionHandler: Add base support for the= #VC exception
   UefiCpuPkg/CpuExceptionHandler: Add support for IOIO_PRO= T NAE events
   UefiCpuPkg/CpuExceptionHandler: Support string IO for IO= IO_PROT NAE
     events
   UefiCpuPkg/CpuExceptionHandler: Add support for CPUID NA= E events
   UefiCpuPkg/CpuExceptionHandler: Add support for MSR_PROT= NAE events
   UefiCpuPkg/CpuExceptionHandler: Add support for NPF NAE = events (MMIO)
   UefiCpuPkg/CpuExceptionHandler: Add support for WBINVD N= AE events
   UefiCpuPkg/CpuExceptionHandler: Add support for RDTSC NA= E events
   UefiCpuPkg/CpuExceptionHandler: Add support for RDPMC NA= E events
   UefiCpuPkg/CpuExceptionHandler: Add support for INVD NAE= events
   UefiCpuPkg/CpuExceptionHandler: Add support for VMMCALL = NAE events
   UefiCpuPkg/CpuExceptionHandler: Add support for RDTSCP N= AE events
   UefiCpuPkg/CpuExceptionHandler: Add support for MONITOR/= MONITORX NAE
     events
   UefiCpuPkg/CpuExceptionHandler: Add support for MWAIT/MW= AITX NAE
     events
   UefiCpuPkg/CpuExceptionHandler: Add support for DR7 Read= /Write NAE
     events
   OvmfPkg/MemEncryptSevLib: Add an SEV-ES guest indicator = function
   OvmfPkg: Add support to perform SEV-ES initialization    OvmfPkg: Create a GHCB page for use during Sec phase
   OvmfPkg/PlatformPei: Reserve GHCB-related areas if S3 is= supported
   OvmfPkg: Create GHCB pages for use during Pei and Dxe ph= ase
   OvmfPkg/PlatformPei: Move early GDT into ram when SEV-ES= is enabled
   UefiCpuPkg: Create an SEV-ES workarea PCD
   OvmfPkg: Reserve a page in memory for the SEV-ES usage    OvmfPkg/ResetVector: Add support for a 32-bit SEV check<= br>    OvmfPkg/Sec: Add #VC exception handling for Sec phase    OvmfPkg/Sec: Enable cache early to speed up booting
   OvmfPkg/QemuFlashFvbServicesRuntimeDxe: Bypass flash det= ection with
     SEV-ES is enabled
   UefiCpuPkg: Add a 16-bit protected mode code segment des= criptor
   UefiCpuPkg/MpInitLib: Add CPU MP data flag to indicate i= f SEV-ES is
     enabled
   UefiCpuPkg: Allow AP booting under SEV-ES
   OvmfPkg: Use the SEV-ES work area for the SEV-ES AP rese= t vector
   OvmfPkg: Move the GHCB allocations into reserved memory<= br>    UefiCpuPkg/MpInitLib: Prepare SEV-ES guest APs for OS us= e

  MdeModulePkg/MdeModulePkg.dec      &n= bsp;          |  &nb= sp; 9 +
  OvmfPkg/OvmfPkg.dec        =             &nb= sp;      |    9 +
  UefiCpuPkg/UefiCpuPkg.dec       =             &nb= sp; |   17 +
  OvmfPkg/OvmfPkgIa32.dsc       &n= bsp;            = ;   |    6 +
  OvmfPkg/OvmfPkgIa32X64.dsc       = ;            &n= bsp;|    6 +
  OvmfPkg/OvmfPkgX64.dsc       &nb= sp;            =     |    6 +
  OvmfPkg/OvmfXen.dsc        =             &nb= sp;      |    1 +
  UefiCpuPkg/UefiCpuPkg.dsc       =             &nb= sp; |    2 +
  UefiPayloadPkg/UefiPayloadPkgIa32.dsc     =     |    2 +
  UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc    &nb= sp; |    2 +
  OvmfPkg/OvmfPkgX64.fdf       &nb= sp;            =     |    9 +
  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf    &nbs= p;  |    2 +
  MdePkg/Library/BaseLib/BaseLib.inf     &nb= sp;      |    4 +
  OvmfPkg/PlatformPei/PlatformPei.inf     &n= bsp;     |    7 +
  .../FvbServicesRuntimeDxe.inf      &n= bsp;          |  &nb= sp; 2 +
  OvmfPkg/ResetVector/ResetVector.inf     &n= bsp;     |    8 +
  OvmfPkg/Sec/SecMain.inf       &n= bsp;            = ;   |    4 +
  .../DxeCpuExceptionHandlerLib.inf     &nbs= p;       |    5 +
  .../PeiCpuExceptionHandlerLib.inf     &nbs= p;       |    5 +
  .../SecPeiCpuExceptionHandlerLib.inf     &= nbsp;    |    5 +
  .../SmmCpuExceptionHandlerLib.inf     &nbs= p;       |    5 +
  UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf |   &n= bsp;4 +
  UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf |   &n= bsp;4 +
  UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf  |  &nb= sp;33 +
  .../Core/DxeIplPeim/X64/VirtualMemory.h    &nbs= p;  |   12 +-
  MdePkg/Include/Library/BaseLib.h      = ;        |   31 +
  MdePkg/Include/Register/Amd/Fam17Msr.h     = ;   |   42 +
  MdePkg/Include/Register/Amd/Ghcb.h     &nb= sp;      |  136 ++
  OvmfPkg/Include/Library/MemEncryptSevLib.h    |=   12 +
  .../QemuFlash.h        &nbs= p;            &= nbsp;         |   13= +
  UefiCpuPkg/CpuDxe/CpuGdt.h       = ;            &n= bsp;|    4 +-
  UefiCpuPkg/Include/Library/VmgExitLib.h    &nbs= p;  |  117 ++
  .../CpuExceptionHandlerLib/AMDSevVcCommon.h   | &nbs= p; 49 +
  .../CpuExceptionCommon.h       &= nbsp;           &nbs= p;  |    2 +
  UefiCpuPkg/Library/MpInitLib/MpLib.h     &= nbsp;    |   68 +-
  .../Core/DxeIplPeim/Ia32/DxeLoadFunc.c     = ;   |    4 +-
  .../Core/DxeIplPeim/X64/DxeLoadFunc.c     =     |   11 +-
  .../Core/DxeIplPeim/X64/VirtualMemory.c    &nbs= p;  |   57 +-
  MdePkg/Library/BaseLib/Ia32/GccInline.c    &nbs= p;  |   45 +
  MdePkg/Library/BaseLib/X64/GccInline.c     = ;   |   47 +
  .../MemEncryptSevLibInternal.c      &= nbsp;         |   75= +-
  OvmfPkg/PlatformPei/AmdSev.c      &nb= sp;           | &nbs= p; 89 +
  OvmfPkg/PlatformPei/MemDetect.c      =          |   23 += ;
  .../QemuFlash.c        &nbs= p;            &= nbsp;         |   23= +-
  .../QemuFlashDxe.c        &= nbsp;           &nbs= p;       |   22 +
  .../QemuFlashSmm.c        &= nbsp;           &nbs= p;       |   16 +
  OvmfPkg/Sec/SecMain.c       &nbs= p;            &= nbsp;    |  188 +-
  UefiCpuPkg/CpuDxe/CpuGdt.c       = ;            &n= bsp;|    8 +-
  .../CpuExceptionHandlerLib/AMDSevVcHandler.c  |  &nb= sp;40 +
  .../CpuExceptionCommon.c       &= nbsp;           &nbs= p;  |    2 +-
  .../Ia32/ArchAMDSevVcHandler.c      &= nbsp;         |   38= +
  .../PeiDxeSmmCpuException.c      &nbs= p;            |=   16 +
  .../SecPeiCpuException.c       &= nbsp;           &nbs= p;  |   16 +
  .../X64/ArchAMDSevVcHandler.c      &n= bsp;          | 1699 += ;+++++++++++++++= ;+
  UefiCpuPkg/Library/MpInitLib/DxeMpLib.c    &nbs= p;  |  113 +-
  UefiCpuPkg/Library/MpInitLib/MpLib.c     &= nbsp;    |  265 ++-
  UefiCpuPkg/Library/MpInitLib/PeiMpLib.c    &nbs= p;  |   19 +
  UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c    |=  293 +++
  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c  |  &nb= sp; 2 +-
  MdeModulePkg/MdeModulePkg.uni      &n= bsp;          |  &nb= sp; 8 +
  MdePkg/Library/BaseLib/Ia32/VmgExit.nasm    &nb= sp; |   37 +
  MdePkg/Library/BaseLib/Ia32/XGetBv.nasm    &nbs= p;  |   31 +
  MdePkg/Library/BaseLib/X64/VmgExit.nasm    &nbs= p;  |   32 +
  MdePkg/Library/BaseLib/X64/XGetBv.nasm     = ;   |   34 +
  OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm  |  100= +
  OvmfPkg/ResetVector/Ia32/PageTables64.asm    &n= bsp;|  350 +++-
  OvmfPkg/ResetVector/ResetVector.nasmb     =     |   20 +
  .../X64/ExceptionHandlerAsm.nasm      = ;        |   17 +
  UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc   | &nbs= p;  2 +-
  .../Library/MpInitLib/Ia32/MpFuncs.nasm    &nbs= p;  |   15 +
  UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc    |=    4 +-
  UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm |  370 += ;++-
  UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni  |  &nb= sp;15 +
  .../ResetVector/Vtf0/Ia16/Real16ToFlat32.asm  |  &nb= sp; 9 +
  UefiCpuPkg/UefiCpuPkg.uni       =             &nb= sp; |   11 +
  75 files changed, 4707 insertions(+), 102 deletions(-)
  create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.in= f
  create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h
  create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h
  create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/A= MDSevVcCommon.h
  create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/A= MDSevVcHandler.c
  create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/I= a32/ArchAMDSevVcHandler.c
  create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X= 64/ArchAMDSevVcHandler.c
  create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c<= br>   create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm   create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm
  create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm
  create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm
  create mode 100644 OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.as= m
  create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.un= i



 

--_000_734D49CCEBEEF84792F5B80ED585239D5C535775SHSMSX104ccrcor_--