From: "Ni, Ray" <ray.ni@intel.com>
To: "Javeed, Ashraf" <ashraf.javeed@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Wang, Jian J" <jian.j.wang@intel.com>, "Wu, Hao A" <hao.a.wu@intel.com>
Subject: Re: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/15] MdeModulePkg/PciBusDxe: Refactor the PCIe Bridge enable
Date: Wed, 13 May 2020 06:31:53 +0000 [thread overview]
Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C53AD1D@SHSMSX104.ccr.corp.intel.com> (raw)
In-Reply-To: <20200510161412.13832-5-ashraf.javeed@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
> -----Original Message-----
> From: Javeed, Ashraf <ashraf.javeed@intel.com>
> Sent: Monday, May 11, 2020 12:14 AM
> To: devel@edk2.groups.io
> Cc: Ni, Ray <ray.ni@intel.com>; Wang, Jian J <jian.j.wang@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/15] MdeModulePkg/PciBusDxe: Refactor the PCIe Bridge enable
>
> REF:
> https://bugzilla.tianocore.org/show_bug.cgi?id=1954
> https://bugzilla.tianocore.org/show_bug.cgi?id=2194
> https://bugzilla.tianocore.org/show_bug.cgi?id=2313
> https://bugzilla.tianocore.org/show_bug.cgi?id=2499
> https://bugzilla.tianocore.org/show_bug.cgi?id=2500
>
> Refactor the PCIe Bridge enabling code.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Jian J Wang <jian.j.wang@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> ---
> MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 70 ++++++++++++++++++++--------------------------------------------------
> 1 file changed, 20 insertions(+), 50 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> index 5724fd6..62ef184 100644
> --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c
> @@ -597,52 +597,36 @@ DeRegisterPciDevice (
> }
>
> /**
> - Start the PCI root Ports or PCI-PCI Bridge only.
> + Enable all the PCI bridges under the specified root bridge or PCI-PCI Bridge.
>
> - @param Controller The root bridge handle.
> - @param RootBridge A pointer to the PCI_IO_DEVICE.
> - @param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL.
> - @param NumberOfChildren Children number.
> - @param ChildHandleBuffer A pointer to the child handle buffer.
> -
> - @retval EFI_NOT_READY Device is not allocated.
> - @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge.
> - @retval EFI_NOT_FOUND Can not find the specific device.
> - @retval EFI_SUCCESS Success to start Pci devices on bridge.
> + @param Bridge A pointer to the PCI_IO_DEVICE.
>
> **/
> -EFI_STATUS
> +VOID
> EnablePciBridges (
> - IN EFI_HANDLE Controller,
> - IN PCI_IO_DEVICE *RootBridge
> + IN PCI_IO_DEVICE *Bridge
> )
>
> {
> PCI_IO_DEVICE *PciIoDevice;
> - EFI_STATUS Status;
> - LIST_ENTRY *CurrentLink;
> + LIST_ENTRY *Link;
> UINT64 Supports;
>
> - PciIoDevice = NULL;
> - CurrentLink = RootBridge->ChildList.ForwardLink;
> -
> - while (CurrentLink != NULL && CurrentLink != &RootBridge->ChildList) {
> -
> - PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
> -
> + for ( Link = GetFirstNode (&Bridge->ChildList)
> + ; !IsNull (&Bridge->ChildList, Link)
> + ; Link = GetNextNode (&Bridge->ChildList, Link)
> + ) {
> + PciIoDevice = PCI_IO_DEVICE_FROM_LINK (Link);
> //
> - // check if the device has been assigned with required resource
> - // and registered
> + // Skip the device hasn't been assigned with required resource
> + // or registered.
> //
> - if (!PciIoDevice->Registered && !PciIoDevice->Allocated) {
> - return EFI_NOT_READY;
> + if (!PciIoDevice->Registered || !PciIoDevice->Allocated) {
> + continue;
> }
>
> if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
> - Status = EnablePciBridges (
> - Controller,
> - PciIoDevice
> - );
> + EnablePciBridges (PciIoDevice);
>
> PciIoDevice->PciIo.Attributes (
> &(PciIoDevice->PciIo),
> @@ -650,27 +634,17 @@ EnablePciBridges (
> 0,
> &Supports
> );
> - Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
> + Supports &= (UINT64) EFI_PCI_DEVICE_ENABLE;
> PciIoDevice->PciIo.Attributes (
> &(PciIoDevice->PciIo),
> EfiPciIoAttributeOperationEnable,
> Supports,
> NULL
> );
> -
> }
> -
> - CurrentLink = CurrentLink->ForwardLink;
> - }
> -
> - if (PciIoDevice == NULL) {
> - return EFI_NOT_FOUND;
> - } else {
> - return EFI_SUCCESS;
> }
> }
>
> -
> /**
> Register to manage the PCI device on the specified root bridge or PCI-PCI Bridge.
>
> @@ -851,9 +825,7 @@ StartPciDevicesOnBridge (
> ChildHandleBuffer
> );
>
> - if (EFI_ERROR (Status)) {
> - return Status;
> - } else {
> + if (!EFI_ERROR (Status)) {
> //
> // the late configuration of PCI Express features
> // the platform is required to indicate its requirement for the initialization
> @@ -861,13 +833,11 @@ StartPciDevicesOnBridge (
> //
>
> //
> - // finally start those PCI bridge port devices only
> + // finally enable those PCI bridges
> //
> - return EnablePciBridges (
> - Controller,
> - RootBridge
> - );
> + EnablePciBridges (RootBridge);
> }
> + return Status;
> }
>
> /**
> --
> 2.21.0.windows.1
next prev parent reply other threads:[~2020-05-13 6:31 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200510161412.13832-1-ashraf.javeed@intel.com>
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/15] MdePkg/Protocols: Deprecated the EFI encoded macros Javeed, Ashraf
2020-05-13 8:21 ` Ni, Ray
2020-05-10 16:13 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/15] MdeModulePkg/PciBus: Rename Cache PCIe Capability Structure Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/15] MdeModulePkg/PciBusDxe: Refactor the PCIe Bridge enable Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray [this message]
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/15] MdeModulePkg/PciBusDxe: Locate PciePlatform/PcieOverride protocol Javeed, Ashraf
2020-05-13 6:31 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/15] MdeModulePkg/PciBusDxe: Add the framework to init PCIe features Javeed, Ashraf
2020-05-13 6:39 ` Ni, Ray
2020-05-13 6:46 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/15] MdeModulePkg/PciBusDxe: Enable MaxPayloadSize feature Javeed, Ashraf
2020-05-13 6:45 ` Ni, Ray
2020-05-13 6:54 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/15] MdeModulePkg/PciBusDxe: Enable MaxReadRequestSize feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/15] MdeModulePkg/PciBusDxe: Enable RelaxedOrdering feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/15] MdeModulePkg/PciBusDxe: Enable NoSnoop feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/15] MdeModulePkg/PciBusDxe: Enable CompletionTimeout feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/15] MdeModulePkg/PciBusDxe: Enable LTR feature Javeed, Ashraf
2020-05-13 6:49 ` Ni, Ray
2020-05-13 7:10 ` Javeed, Ashraf
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 13/15] MdeModulePkg/PciBusDxe: Enable AtomicOp feature Javeed, Ashraf
2020-05-13 6:51 ` [edk2-devel] " Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 14/15] MdeModulePkg/PciBusDxe: Enable ExtendedTag feature Javeed, Ashraf
2020-05-13 8:09 ` [edk2-devel] " Ni, Ray
2020-05-10 16:14 ` [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 15/15] MdeModulePkg/PciBusDxe: Enable CommonClockConfiguration feature Javeed, Ashraf
2020-05-13 8:19 ` Ni, Ray
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=734D49CCEBEEF84792F5B80ED585239D5C53AD1D@SHSMSX104.ccr.corp.intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox