From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com []) by mx.groups.io with SMTP id smtpd.web12.959.1589351518531299375 for ; Tue, 12 May 2020 23:32:02 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) IronPort-SDR: dP8GmW5LpoeyqiJ08HilmpUClSUeUbeUSawd5StvGipjqpvHK+7Y4Xb4Q2FLQV0SpQCJQkCSx7 Ggc2yBeUHz+w== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2020 23:32:01 -0700 IronPort-SDR: p0IoV3uV0Wb7Wx2GsH6eY1XZLXF0yZ7DO8HeGA0GoCIeRYRrugFnCReYIgzt5xD4pB0qU1vKSV CdGtnHO+5O7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,386,1583222400"; d="scan'208";a="253105624" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga008.fm.intel.com with ESMTP; 12 May 2020 23:32:00 -0700 Received: from fmsmsx158.amr.corp.intel.com (10.18.116.75) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:32:00 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx158.amr.corp.intel.com (10.18.116.75) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 12 May 2020 23:32:00 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.225]) with mapi id 14.03.0439.000; Wed, 13 May 2020 14:31:54 +0800 From: "Ni, Ray" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" Subject: Re: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Thread-Topic: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBusDxe: PciBusDxe Code refactor Thread-Index: AQHWJuYUJe62JSGvi0ytnelqFKTApKig+B2AgASaEkA= Date: Wed, 13 May 2020 06:31:53 +0000 Deferred-Delivery: Wed, 13 May 2020 06:31:00 +0000 Message-ID: <734D49CCEBEEF84792F5B80ED585239D5C53AD22@SHSMSX104.ccr.corp.intel.com> References: <20200510161412.13832-1-ashraf.javeed@intel.com> <20200510161412.13832-3-ashraf.javeed@intel.com> In-Reply-To: <20200510161412.13832-3-ashraf.javeed@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: ray.ni@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Javeed, Ashraf > Sent: Monday, May 11, 2020 12:14 AM > To: devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A ;= Ni, Ray > Subject: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/15] MdeModulePkg/PciBu= sDxe: PciBusDxe Code refactor >=20 > References:- > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2499 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D2500 >=20 > This code change represents the code refactoring by expelling the > previous changes of the PCIe features. >=20 > Signed-off-by: Ashraf Javeed > Cc: Jian J Wang > Cc: Hao A Wu > Cc: Ray Ni > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 4 -- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 20 ++------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 10 +---- > MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 11 +---- > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c | 2178 -------------= -------------------------------------------------------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h | 399 -------------= --------------------------------------------------------------------- > -------------------------------------------------------------------------= ----------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 1019 -------------= -------------------------------------------------------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > ---------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 304 -------------= --------------------------------------------------------------------- > ------------------------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 902 -------------= --------------------------------------------------------------------- > -------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------- > -------------------------------------------------------------------------= --------------------------------------------------------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 119 -------------= --------------------------------------- > 10 files changed, 6 insertions(+), 4960 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/P= ci/PciBusDxe/PciBus.c > index 714101c..53e6dfa 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c > @@ -284,10 +284,6 @@ PciBusDriverBindingStart ( > (VOID **) &gPciOverrideProtocol >=20 > ); >=20 > } >=20 > - // >=20 > - // get the PCI Express Protocol or the PCI Express Override Protocol >=20 > - // >=20 > - GetPciExpressProtocol (); >=20 >=20 >=20 > if (mIoMmuProtocol =3D=3D NULL) { >=20 > gBS->LocateProtocol ( >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/P= ci/PciBusDxe/PciBus.h > index 34f482d..5a7c1c2 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -27,6 +27,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include >=20 > #include >=20 > #include >=20 > +#include >=20 > +#include >=20 >=20 >=20 > #include >=20 > #include >=20 > @@ -42,8 +44,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include >=20 > #include >=20 > #include >=20 > -#include >=20 > -#include >=20 > + >=20 >=20 >=20 > typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE; >=20 > typedef struct _PCI_BAR PCI_BAR; >=20 > @@ -81,8 +82,6 @@ typedef enum { > #include "PciPowerManagement.h" >=20 > #include "PciHotPlugSupport.h" >=20 > #include "PciLib.h" >=20 > -#include "PciPlatformSupport.h" >=20 > -#include "PciFeatureSupport.h" >=20 >=20 >=20 > #define VGABASE1 0x3B0 >=20 > #define VGALIMIT1 0x3BB >=20 > @@ -287,19 +286,6 @@ struct _PCI_IO_DEVICE { > // This field is used to support this case. >=20 > // >=20 > UINT16 BridgeIoAlignment; >=20 > - // >=20 > - // PCI Express features setup flags >=20 > - // >=20 > - UINT8 SetupMPS; >=20 > - UINT8 SetupMRRS; >=20 > - PCI_FEATURE_POLICY SetupRO; >=20 > - PCI_FEATURE_POLICY SetupNS; >=20 > - PCI_FEATURE_POLICY SetupCTO; >=20 > - EFI_PCI_EXPRESS_ATOMIC_OP SetupAtomicOp; >=20 > - BOOLEAN SetupLtr; >=20 > - UINT8 SetupExtTag; >=20 > - UINT8 SetupAspm; >=20 > - EFI_PCI_EXPRESS_COMMON_CLOCK_CFG SetupCcc; >=20 > }; >=20 >=20 >=20 > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/= Bus/Pci/PciBusDxe/PciBusDxe.inf > index e3ad105..3b1559e 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -57,12 +57,6 @@ > PciCommand.h >=20 > PciIo.h >=20 > PciBus.h >=20 > - PciFeatureSupport.c >=20 > - PciFeatureSupport.h >=20 > - PciPlatformSupport.c >=20 > - PciPlatformSupport.h >=20 > - PciExpressFeatures.c >=20 > - PciExpressFeatures.h >=20 >=20 >=20 > [Packages] >=20 > MdePkg/MdePkg.dec >=20 > @@ -97,8 +91,8 @@ > gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES >=20 > gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES >=20 > gEfiLoadedImageDevicePathProtocolGuid ## CONSUMES >=20 > - gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CO= NSUMES >=20 > - gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CO= NSUMES >=20 > + gEfiPciExpressPlatformProtocolGuid ## SOMETIMES_CONSUMES >=20 > + gEfiPciExpressOverrideProtocolGuid ## SOMETIMES_CONSUMES >=20 >=20 >=20 >=20 >=20 > [FeaturePcd] >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > index 07ee9ba..5724fd6 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c > @@ -859,16 +859,7 @@ StartPciDevicesOnBridge ( > // the platform is required to indicate its requirement for the init= ialization >=20 > // of PCI Express features by publishing its protocol >=20 > // >=20 > - if ( >=20 > - gFullEnumeration >=20 > - && IsPciExpressProtocolPresent () >=20 > - ) { >=20 > - >=20 > - Status =3D EnumeratePciExpressFeatures ( >=20 > - Controller, >=20 > - RootBridge >=20 > - ); >=20 > - } >=20 > + >=20 > // >=20 > // finally start those PCI bridge port devices only >=20 > // >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > deleted file mode 100644 > index 1e2f4a4..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.c > +++ /dev/null > @@ -1,2178 +0,0 @@ > -/** @file >=20 > - PCI standard feature support functions implementation for PCI Bus modu= le.. >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > -#include "PciBus.h" >=20 > -#include "PciFeatureSupport.h" >=20 > - >=20 > -VOID >=20 > -ReportPciWriteError ( >=20 > - IN UINT8 Bus, >=20 > - IN UINT8 Device, >=20 > - IN UINT8 Function, >=20 > - IN UINT32 Offset >=20 > - ) >=20 > -{ >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "Unexpected PCI register (%d,%d,%d,0x%x) write error!", >=20 > - Bus, >=20 > - Device, >=20 > - Function, >=20 > - Offset >=20 > - )); >=20 > -} >=20 > - >=20 > -/** >=20 > - Compare and Swap the payload value - between the global variable to ma= aintain >=20 > - common value among all the devices in the PCIe heirarchy from the root= bridge >=20 > - device and all its child devices; with the device-sepcific setup value= . >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature Max_Pa= yload_Size >=20 > - is successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -CasMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfigurati= onTable >=20 > - ) >=20 > -{ >=20 > - UINT8 MpsValue; >=20 > - >=20 > - // >=20 > - // align the MPS of the tree to the HCF with this device >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - MpsValue =3D PciExpressConfigurationTable->Max_Payload_Size; >=20 > - >=20 > - MpsValue =3D MIN (PciDevice->SetupMPS, MpsValue); >=20 > - PciDevice->SetupMPS =3D MIN (PciDevice->SetupMPS, MpsValue); >=20 > - >=20 > - if (MpsValue !=3D PciExpressConfigurationTable->Max_Payload_Size) { >=20 > - PciExpressConfigurationTable->Max_Payload_Size =3D MpsValue; >=20 > - } >=20 > - } >=20 > - >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "MPS: %d [DevCap:%d],", >=20 > - PciDevice->SetupMPS, PciDevice->PciExpressCapabilityStructure.Device= Capability.Bits.MaxPayloadSize >=20 > - )); >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature Max_Payload_Size as per= the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4, that aligns the value for the entire PCI hei= rarchy >=20 > - starting from its physical PCI Root port / Bridge device. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature Max_Pa= yload_Size >=20 > - is successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; >=20 > - UINT8 MpsValue; >=20 > - >=20 > - >=20 > - PciDeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.Devic= eCapability.Uint32; >=20 > - >=20 > - if (PciDevice->SetupMPS =3D=3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO) = { >=20 > - // >=20 > - // configure this feature as per its PCIe device capabilities >=20 > - // >=20 > - MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; >=20 > - // >=20 > - // no change to PCI Root ports without any endpoint device >=20 > - // >=20 > - if (IS_PCI_BRIDGE (&PciDevice->Pci) && PciDeviceCap.Bits.MaxPayloadS= ize) { >=20 > - if (IsListEmpty (&PciDevice->ChildList)) { >=20 > - // >=20 > - // No device on root bridge >=20 > - // >=20 > - MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; >=20 > - } >=20 > - } >=20 > - } else { >=20 > - MpsValue =3D SetDevicePolicyPciExpressMps (PciDevice->SetupMPS); >=20 > - } >=20 > - // >=20 > - // discard device policy override request if greater than PCI device c= apability >=20 > - // >=20 > - PciDevice->SetupMPS =3D MIN ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, = MpsValue); >=20 > - >=20 > - return CasMaxPayloadSize ( >=20 > - PciDevice, >=20 > - PciExpressConfigurationTable >=20 > - ); >=20 > -} >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register MaxPayloadSize register fiel= d; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) { >=20 > - PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS; >=20 > - DEBUG (( DEBUG_INFO, "MPS=3D%d,", PciDevice->SetupMPS)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D = PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "No MPS=3D%d,", PciDevice->SetupMPS)); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -EFI_STATUS >=20 > -ConditionalCasMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // align the Max_Read_Request_Size of the PCI tree based on 3 conditio= ns: >=20 > - // first, if user defines MRRS for any one PCI device in the tree than= align >=20 > - // all the devices in the PCI tree. >=20 > - // second, if user override is not define for this PCI tree than setup= the MRRS >=20 > - // based on MPS value of the tree to meet the criteria for the isochro= nous >=20 > - // traffic. >=20 > - // third, if no user override, or platform firmware policy has not sel= ected >=20 > - // this PCI bus driver to configure the MPS; than configure the MRRS t= o a >=20 > - // highest common value of PCI device capability for the MPS found amo= ng all >=20 > - // the PCI devices in this tree >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - if (PciExpressConfigurationTable->Lock_Max_Read_Request_Size) { >=20 > - PciDevice->SetupMRRS =3D PciExpressConfigurationTable->Max_Read_Re= quest_Size; >=20 > - } else { >=20 > - if (mPciExpressPlatformPolicy.Mps) { >=20 > - PciDevice->SetupMRRS =3D PciDevice->SetupMPS; >=20 > - } else { >=20 > - PciDevice->SetupMRRS =3D MIN ( >=20 > - PciDevice->SetupMRRS, >=20 > - PciExpressConfigurationTable->Max_Read_R= equest_Size >=20 > - ); >=20 > - } >=20 > - PciExpressConfigurationTable->Max_Read_Request_Size =3D PciDevice-= >SetupMRRS; >=20 > - } >=20 > - } >=20 > - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS)); >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature Max_Read_Req_Size as pe= r the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4, that aligns the value for the entire PCI hei= rarchy >=20 > - starting from its physical PCI Root port / Bridge device. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature Max_Re= ad_Req_Size >=20 > - is successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; >=20 > - UINT8 MrrsValue; >=20 > - >=20 > - PciDeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.Devic= eCapability.Uint32; >=20 > - >=20 > - if (PciDevice->SetupMRRS =3D=3D EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO= ) { >=20 > - // >=20 > - // The maximum read request size is not the data packet size of the = TLP, >=20 > - // but the memory read request size, and set to the function as a re= questor >=20 > - // to not exceed this limit. >=20 > - // However, for the PCI device capable of isochronous traffic; this = memory read >=20 > - // request size should not extend beyond the Max_Payload_Size. Thus,= in case if >=20 > - // device policy return by platform indicates to set as per device c= apability >=20 > - // than set as per Max_Payload_Size configuration value >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Mps) { >=20 > - MrrsValue =3D PciDevice->SetupMPS; >=20 > - } else { >=20 > - // >=20 > - // in case this driver is not required to configure the Max_Payloa= d_Size >=20 > - // than consider programming HCF of the device capability's Max_Pa= yload_Size >=20 > - // in this PCI hierarchy; thus making this an implementation speci= fic feature >=20 > - // which the platform should avoid. For better results, the platfo= rm should >=20 > - // make both the Max_Payload_Size & Max_Read_Request_Size to be co= nfigured >=20 > - // by this driver >=20 > - // >=20 > - MrrsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // override as per platform based device policy >=20 > - // >=20 > - MrrsValue =3D SetDevicePolicyPciExpressMrrs (PciDevice->SetupMRRS); >=20 > - // >=20 > - // align this device's Max_Read_Request_Size value to the entire PCI= tree >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - if (!PciExpressConfigurationTable->Lock_Max_Read_Request_Size) { >=20 > - PciExpressConfigurationTable->Lock_Max_Read_Request_Size =3D TRU= E; >=20 > - PciExpressConfigurationTable->Max_Read_Request_Size =3D MrrsValu= e; >=20 > - } else { >=20 > - // >=20 > - // in case of another user enforced value of MRRS within the sam= e tree, >=20 > - // pick the smallest between the locked value and this value; to= set >=20 > - // across entire PCI tree nodes >=20 > - // >=20 > - MrrsValue =3D MIN ( >=20 > - MrrsValue, >=20 > - PciExpressConfigurationTable->Max_Read_Request_Siz= e >=20 > - ); >=20 > - PciExpressConfigurationTable->Max_Read_Request_Size =3D MrrsValu= e; >=20 > - } >=20 > - } >=20 > - } >=20 > - // >=20 > - // align this device's Max_Read_Request_Size to derived configuration = value >=20 > - // >=20 > - PciDevice->SetupMRRS =3D MrrsValue; >=20 > - >=20 > - return ConditionalCasMaxReadReqSize ( >=20 > - PciDevice, >=20 > - PciExpressConfigurationTable >=20 > - ); >=20 > -} >=20 > - >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register Max_Read_Req_Size register f= ield; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI controller. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PcieDev.Bits.MaxReadRequestSize !=3D PciDevice->SetupMRRS) { >=20 > - PcieDev.Bits.MaxReadRequestSize =3D PciDevice->SetupMRRS; >=20 > - DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D = PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "No MRRS=3D%d,", PciDevice->SetupMRRS)); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register Relax Order register field; = if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramRelaxOrder ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PciDevice->SetupRO.Override >=20 > - && PcieDev.Bits.RelaxedOrdering !=3D PciDevice->SetupRO.Act >=20 > - ) { >=20 > - PcieDev.Bits.RelaxedOrdering =3D PciDevice->SetupRO.Act; >=20 > - DEBUG (( DEBUG_INFO, "RO=3D%d,", PciDevice->SetupRO.Act)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D = PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "No RO,", PciDevice->SetupRO.Act)); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register No-Snoop register field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramNoSnoop ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PciDevice->SetupNS.Override >=20 > - && PcieDev.Bits.NoSnoop !=3D PciDevice->SetupNS.Act >=20 > - ) { >=20 > - PcieDev.Bits.NoSnoop =3D PciDevice->SetupNS.Act; >=20 > - DEBUG (( DEBUG_INFO, "NS=3D%d", PciDevice->SetupNS.Act)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D = PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "No NS,", PciDevice->SetupRO.Act)); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - To determine the CTO Range A values >=20 > - >=20 > - @param CtoValue input CTO range value from 0 to 14 >=20 > - @retval TRUE the given CTO value belongs to Range A >=20 > - FALSE the given value does not belong to Range A >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsCtoRangeA ( >=20 > - IN UINT8 CtoValue >=20 > - ) >=20 > -{ >=20 > - switch (CtoValue) { >=20 > - case PCIE_COMPLETION_TIMEOUT_50US_100US: >=20 > - case PCIE_COMPLETION_TIMEOUT_1MS_10MS: >=20 > - return TRUE; >=20 > - } >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - To determine the CTO Range B values >=20 > - >=20 > - @param CtoValue input CTO range value from 0 to 14 >=20 > - @retval TRUE the given CTO value belongs to Range B >=20 > - FALSE the given value does not belong to Range B >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsCtoRangeB ( >=20 > - IN UINT8 CtoValue >=20 > - ) >=20 > -{ >=20 > - switch (CtoValue) { >=20 > - case PCIE_COMPLETION_TIMEOUT_16MS_55MS: >=20 > - case PCIE_COMPLETION_TIMEOUT_65MS_210MS: >=20 > - return TRUE; >=20 > - } >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - To determine the CTO Range C values >=20 > - >=20 > - @param CtoValue input CTO range value from 0 to 14 >=20 > - @retval TRUE the given CTO value belongs to Range C >=20 > - FALSE the given value does not belong to Range C >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsCtoRangeC ( >=20 > - IN UINT8 CtoValue >=20 > - ) >=20 > -{ >=20 > - switch (CtoValue) { >=20 > - case PCIE_COMPLETION_TIMEOUT_260MS_900MS: >=20 > - case PCIE_COMPLETION_TIMEOUT_1S_3_5S: >=20 > - return TRUE; >=20 > - } >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - To determine the CTO Range D values >=20 > - >=20 > - @param CtoValue input CTO range value from 0 to 14 >=20 > - @retval TRUE the given CTO value belongs to Range D >=20 > - FALSE the given value does not belong to Range D >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsCtoRangeD ( >=20 > - IN UINT8 CtoValue >=20 > - ) >=20 > -{ >=20 > - switch (CtoValue) { >=20 > - case PCIE_COMPLETION_TIMEOUT_4S_13S: >=20 > - case PCIE_COMPLETION_TIMEOUT_17S_64S: >=20 > - return TRUE; >=20 > - } >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine which setup the PCI feature Completion Timeout as per= the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature CTO is= successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupCompletionTimeout ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; >=20 > - UINT8 CtoRangeValue; >=20 > - >=20 > - if (!PciDevice->SetupCTO.Override) { >=20 > - // >=20 > - // No override of CTO is required for this device >=20 > - // >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // determine the CTO range values as per its device capability registe= r >=20 > - // >=20 > - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability2.Uint32; >=20 > - if (!DeviceCap2.Bits.CompletionTimeoutRanges >=20 > - && !DeviceCap2.Bits.CompletionTimeoutDisable >=20 > - ) { >=20 > - // >=20 > - // device does not support the CTO mechanism, hence no override is a= pplicable >=20 > - // >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // override the device CTO values if applicable >=20 > - // >=20 > - if (PciDevice->SetupCTO.Act) { >=20 > - // >=20 > - // program the CTO range values >=20 > - // >=20 > - if (DeviceCap2.Bits.CompletionTimeoutRanges) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - // >=20 > - // in case if the supported CTO range and the requirement from pla= tform >=20 > - // policy does not match, than the CTO range setting would be base= d on >=20 > - // this driver's implementation specific, and its rules are as fol= lows:- >=20 > - // >=20 > - // if device is capable of Range A only and if platform ask for an= y of >=20 > - // ranges B, C, D; than this implementation will only program the = default >=20 > - // range value for the duration of 50us to 50ms. >=20 > - // >=20 > - // if device is capable of Range B, or range B & C, or Ranges B, C= & D only >=20 > - // and if the platform ask for the Range A; than this implementati= on will >=20 > - // only program the default range value for the duration of 50us t= o 50ms. >=20 > - // >=20 > - // if the device is capable of Range B only, or the ranges A & B; = and the >=20 > - // platform ask for Range C, or Range D values, than this implemen= tation >=20 > - // will only program the Range B value for the duration of 65ms to= 210ms. >=20 > - // >=20 > - // if the device is capable of Ranges B & C, or Ranges A, B, and C= ; and >=20 > - // if the platform ask for Range D values; than this implementatio= n will >=20 > - // only program the Range C for the duration of 1s to 3.5s. >=20 > - // >=20 > - >=20 > - switch (DeviceCap2.Bits.CompletionTimeoutRanges) { >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - // >=20 > - // if device is capable of Range A only and if platform ask fo= r any of >=20 > - // ranges B, C, D; than this implementation will only program = the default >=20 > - // range value for the duration of 50us to 50ms. >=20 > - // >=20 > - if (IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeD (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED: >=20 > - // >=20 > - // if device is capable of Range B, or range B & C, or Ranges = B, C & D only >=20 > - // and if the platform ask for the Range A; than this implemen= tation will >=20 > - // only program the default range value for the duration of 50= us to 50ms. >=20 > - // >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - } >=20 > - >=20 > - if (IsCtoRangeB (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - // >=20 > - // if the device is capable of Range B only, or the ranges A &= B; and the >=20 > - // platform ask for Range C, or Range D values, than this impl= ementation >=20 > - // will only program the Range B value for the duration of 65m= s to 210ms. >=20 > - // >=20 > - if (IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeD (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - } >=20 > - >=20 > - if (IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - // >=20 > - // if the device is capable of Ranges B & C, or Ranges A, B, a= nd C; and >=20 > - // if the platform ask for Range D values; than this implement= ation will >=20 > - // only program the Range C for the duration of 1s to 3.5s. >=20 > - // >=20 > - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - } >=20 > - if (IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeD (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - if (IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeD (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - if (IsCtoRangeD (PciDevice->SetupCTO.Support)) { >=20 > - CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; >=20 > - } >=20 > - break; >=20 > - >=20 > - case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED: >=20 > - if (IsCtoRangeA (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeB (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeC (PciDevice->SetupCTO.Support) >=20 > - || IsCtoRangeD (PciDevice->SetupCTO.Support) >=20 > - ) { >=20 > - CtoRangeValue =3D PciDevice->SetupCTO.Support; >=20 > - } >=20 > - break; >=20 > - >=20 > - default: >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "Invalid CTO range: %d\n", >=20 > - DeviceCap2.Bits.CompletionTimeoutRanges >=20 > - )); >=20 > - return EFI_INVALID_PARAMETER; >=20 > - } >=20 > - >=20 > - if (PciDevice->SetupCTO.Support !=3D CtoRangeValue) { >=20 > - PciDevice->SetupCTO.Support =3D CtoRangeValue; >=20 > - } >=20 > - } >=20 > - DEBUG (( DEBUG_INFO, "CTO enable: %d, CTO range: 0x%x,", >=20 > - PciDevice->SetupCTO.Act, >=20 > - PciDevice->SetupCTO.Support >=20 > - )); >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control2 register Completion Timeout range; i= f >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramCompletionTimeout ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2; >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - if (!PciDevice->SetupCTO.Override) { >=20 > - // >=20 > - // No override of CTO is required for this device >=20 > - // >=20 > - DEBUG (( DEBUG_INFO, "CTO skipped,")); >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // to program the CTO range values, determine in its device capability= register >=20 > - // >=20 > - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability2.Uint32; >=20 > - if (DeviceCap2.Bits.CompletionTimeoutRanges >=20 > - || DeviceCap2.Bits.CompletionTimeoutDisable) { >=20 > - // >=20 > - // device supports the CTO mechanism >=20 > - // >=20 > - DeviceCtl2.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &DeviceCtl2.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - } else { >=20 > - // >=20 > - // device does not support the CTO mechanism, hence no override perf= ormed >=20 > - // >=20 > - DEBUG (( DEBUG_INFO, "CTO n/a,")); >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // override the device CTO values if applicable >=20 > - // >=20 > - if (PciDevice->SetupCTO.Act) { >=20 > - // >=20 > - // program the CTO range values >=20 > - // >=20 > - if (PciDevice->SetupCTO.Support !=3D DeviceCtl2.Bits.CompletionTimeo= utValue) { >=20 > - DeviceCtl2.Bits.CompletionTimeoutValue =3D PciDevice->SetupCTO.Sup= port; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // disable the CTO mechanism in device >=20 > - // >=20 > - DeviceCtl2.Bits.CompletionTimeoutValue =3D 0; >=20 > - DeviceCtl2.Bits.CompletionTimeoutDisable =3D 1; >=20 > - } >=20 > - DEBUG (( DEBUG_INFO, "CTO disable: %d, CTO range: 0x%x,", >=20 > - DeviceCtl2.Bits.CompletionTimeoutDisable, >=20 > - DeviceCtl2.Bits.CompletionTimeoutValue >=20 > - )); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the write = operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &DeviceCtl2.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D D= eviceCtl2.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber, = PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to setup the AtomicOp Requester in the PCI device, verifies th= e routing >=20 > - support in the bridge devices, to be complaint as per the PCI Base spe= cification. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExFeatureConfiguration pointer to common configuration = table to >=20 > - initialize the PCI Express featu= re >=20 > - >=20 > - @retval EFI_SUCCESS bridge device routing capability= is successful. >=20 > - EFI_INVALID_PARAMETER input parameter is NULL >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupAtomicOpRoutingSupport ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfigurati= on >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // to enable the AtomicOp Requester in the PCI EP device; its Root Por= t (bridge), >=20 > - // and its PCIe switch upstream & downstream ports (if present) needs = to support >=20 > - // the AtomicOp Routing capability. >=20 > - // >=20 > - if (IS_PCI_BRIDGE (&PciDevice->Pci)) { >=20 > - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits= .AtomicOpRouting) { >=20 > - // >=20 > - // since the AtomicOp Routing support flag is initialized as TRUE,= negate >=20 > - // in case if any of the PCI Bridge device in the PCI tree does no= t support >=20 > - // the AtomicOp Routing capability >=20 > - // >=20 > - if (PciExFeatureConfiguration =3D=3D NULL) { >=20 > - return EFI_INVALID_PARAMETER; >=20 > - } >=20 > - PciExFeatureConfiguration->AtomicOpRoutingSupported =3D FALSE; >=20 > - } >=20 > - } >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control 2 register AtomicOp Requester enable = field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramAtomicOp ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PciDevice->SetupAtomicOp.Override) { >=20 > - // >=20 > - // override AtomicOp requester device control bit of the device base= d on the >=20 > - // platform request >=20 > - // >=20 > - if (IS_PCI_BRIDGE (&PciDevice->Pci)) { >=20 > - // >=20 > - // for a bridge device as AtomicOp Requester function; only platfo= rm override >=20 > - // request is used to set the device control register >=20 > - // >=20 > - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomicOp.E= nable_AtomicOpRequester) { >=20 > - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.Enab= le_AtomicOpRequester; >=20 > - } >=20 > - // >=20 > - // if platform also request its AtomicOp Egress blocking to be ena= bled; set >=20 > - // only if its device capability's AtomicOpRouting bit is 1. >=20 > - // applicable to only the bridge devices >=20 > - // >=20 > - if (PciDevice->SetupAtomicOp.Enable_AtomicOpEgressBlocking) { >=20 > - if (PciDevice->PciExpressCapabilityStructure.DeviceCapability2.B= its.AtomicOpRouting) { >=20 > - PcieDev.Bits.AtomicOpEgressBlocking =3D 1; >=20 > - } >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // in the case of non-bridge device >=20 > - // >=20 > - if (PciExFeatureConfiguration) { >=20 > - // >=20 > - // for a device as AtomicOp Requester function; its bridge devic= es should >=20 > - // support the AtomicOp Routing capability to enable the device'= s as a >=20 > - // requester function >=20 > - // >=20 > - if (PciExFeatureConfiguration->AtomicOpRoutingSupported) { >=20 > - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomic= Op.Enable_AtomicOpRequester) { >=20 > - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.= Enable_AtomicOpRequester; >=20 > - } >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // for the RCiEP device or the bridge device without any child, = setup AtomicOp >=20 > - // Requester as per platform's device policy >=20 > - // >=20 > - if (PcieDev.Bits.AtomicOpRequester !=3D PciDevice->SetupAtomicOp= .Enable_AtomicOpRequester) { >=20 > - PcieDev.Bits.AtomicOpRequester =3D PciDevice->SetupAtomicOp.En= able_AtomicOpRequester; >=20 > - } >=20 > - } >=20 > - // >=20 > - // the enabling of AtomicOp Egress Blocking is not applicable to a= non-bridge >=20 > - // device >=20 > - // >=20 > - } >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "AtomicOp=3D%d,", >=20 > - PcieDev.Bits.AtomicOpRequester >=20 > - )); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D= PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "No AtomicOp,")); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature LTR enable/disable as p= er the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; >=20 > - // >=20 > - // as per the PCI-Express Base Specification, in order to enable LTR m= echanism >=20 > - // in the upstream ports, all the upstream ports and its downstream po= rts has >=20 > - // to support the LTR mechanism reported in its Device Capability 2 re= gister >=20 > - // >=20 > - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability2.Uint32; >=20 > - >=20 > - if (PciExpressConfigurationTable) { >=20 > - // >=20 > - // in this phase establish 2 requirements: >=20 > - // (1) all the PCI devices in the hierarchy supports the LTR mechani= sm >=20 > - // (2) check and record any device-specific platform policy that wan= ts to >=20 > - // enable the LTR mechanism >=20 > - // >=20 > - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits= .LtrMechanism) { >=20 > - >=20 > - // >=20 > - // it starts with the assumption that all the PCI devices support = LTR mechanism >=20 > - // and negates the flag if any PCI device Device Capability 2 regi= ster advertizes >=20 > - // as not supported >=20 > - // >=20 > - PciExpressConfigurationTable->LtrSupported =3D FALSE; >=20 > - } >=20 > - >=20 > - if (PciDevice->SetupLtr =3D=3D TRUE) { >=20 > - // >=20 > - // it starts with the assumption that device-specific platform pol= icy would >=20 > - // be set to LTR disable, and negates the flag if any PCI device p= latform >=20 > - // policy wants to override to enable the LTR mechanism >=20 > - // >=20 > - PciExpressConfigurationTable->LtrEnable =3D TRUE; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // in case of RCiEP device or the bridge device with out any child d= evice, >=20 > - // overrule the device policy if the device in not capable >=20 > - // >=20 > - if (!PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits= .LtrMechanism >=20 > - && PciDevice->SetupLtr =3D=3D TRUE) { >=20 > - PciDevice->SetupLtr =3D FALSE; >=20 > - } >=20 > - // >=20 > - // for any bridge device which is Hot-Plug capable, it is expected t= hat platform >=20 > - // will not enforce the enabling of LTR mechanism only for the bridg= e device >=20 > - // >=20 > - } >=20 > - >=20 > - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),", >=20 > - PciDevice->SetupLtr ? 1 : 0, >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrM= echanism >=20 > - )); >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -EFI_STATUS >=20 > -ReSetupLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // not applicable to RCiEP device... >=20 > - // for the bridge device without any child device, the policy is alrea= dy overruled >=20 > - // based on capability in the above routine >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - // >=20 > - // in this phase align the device policy to enable LTR policy of any= PCI device >=20 > - // in the tree if all the devices are capable to support the LTR mec= hanism >=20 > - // >=20 > - if (PciExpressConfigurationTable->LtrSupported =3D=3D TRUE >=20 > - && PciExpressConfigurationTable->LtrEnable =3D=3D TRUE >=20 > - ) { >=20 > - PciDevice->SetupLtr =3D TRUE; >=20 > - } else { >=20 > - PciDevice->SetupLtr =3D FALSE; >=20 > - } >=20 > - } >=20 > - >=20 > - DEBUG (( DEBUG_INFO, "LTR En: %d (LTR Cap: %d),", >=20 > - PciDevice->SetupLtr ? 1 : 0, >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceCapability2.Bits.LtrM= echanism >=20 > - )); >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Program the PCI Device Control 2 register LTR mechanism field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL2 PcieDev; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - PcieDev.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - if (PciDevice->SetupLtr !=3D (BOOLEAN) PcieDev.Bits.LtrMechanism) { >=20 > - PcieDev.Bits.LtrMechanism =3D PciDevice->SetupLtr ? 1 : 0; >=20 > - DEBUG (( DEBUG_INFO, "LTR=3D%d,", PcieDev.Bits.LtrMechanism)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &PcieDev.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D= PcieDev.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "no LTR,")); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature Extended Tag as per = the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCap; >=20 > - EFI_PCI_EXPRESS_EXTENDED_TAG PciExpressExtendedTag; >=20 > - >=20 > - DeviceCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceCa= pability.Uint32; >=20 > - DeviceCap2.Uint32 =3D PciDevice->PciExpressCapabilityStructure.DeviceC= apability2.Uint32; >=20 > - // >=20 > - // The PCI Express feature Extended Tag has to be maintained common fr= om a >=20 > - // root bridge device to all its child devices. >=20 > - // The Device Capability 2 register is used to determine the 10b Exten= ded Tag >=20 > - // capability of a device. The device capability register is used to d= etermine >=20 > - // 5b/8b Extended Tag capability of a device >=20 > - // >=20 > - if (DeviceCap2.Bits.TenBitTagCompleterSupported & DeviceCap2.Bits.TenB= itTagRequesterSupported) { >=20 > - // >=20 > - // device supports the 10b Extended Tag capability >=20 > - // >=20 > - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT; >=20 > - } else { >=20 > - if (DeviceCap.Bits.ExtendedTagField) { >=20 > - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT; >=20 > - } else { >=20 > - PciExpressExtendedTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT; >=20 > - } >=20 > - } >=20 > - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO) { >=20 > - PciDevice->SetupExtTag =3D PciExpressExtendedTag; >=20 > - } >=20 > - // >=20 > - // in case of PCI Bridge and its child devices >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - // >=20 > - // align the Extended Tag value as per the device supported value >=20 > - // >=20 > - PciExpressConfigurationTable->ExtendedTag =3D MIN ( >=20 > - PciExpressExtendedTag, >=20 > - PciExpressConfiguratio= nTable->ExtendedTag >=20 > - ); >=20 > - // >=20 > - // check for any invalid platform policy request for the device; if = true than >=20 > - // align with the device capability value. Else align as per platfor= m request >=20 > - // >=20 > - if (PciDevice->SetupExtTag > PciExpressConfigurationTable->ExtendedT= ag) { >=20 > - // >=20 > - // setup the device Extended Tag to common value supported by all = the devices >=20 > - // >=20 > - PciDevice->SetupExtTag =3D PciExpressConfigurationTable->ExtendedT= ag; >=20 > - } >=20 > - // >=20 > - // if the platform policy is to downgrade the device's Extended Tag = value than >=20 > - // all the other devices in the PCI tree including the root bridge w= ill be align >=20 > - // with this device override value >=20 > - // >=20 > - if (PciDevice->SetupExtTag < PciExpressConfigurationTable->ExtendedT= ag) { >=20 > - PciExpressConfigurationTable->ExtendedTag =3D PciDevice->SetupExtT= ag; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // in case of RCiEP devices or the bridge device without any child, = overrule >=20 > - // the Extended Tag device policy if it does not match with its capa= bility >=20 > - // >=20 > - PciDevice->SetupExtTag =3D MIN ( >=20 > - PciDevice->SetupExtTag, >=20 > - PciExpressExtendedTag >=20 > - ); >=20 > - } >=20 > - >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "ExtTag: %d [cap:%d],", >=20 > - PciDevice->SetupExtTag, >=20 > - PciExpressExtendedTag >=20 > - )); >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Additional routine to setup the PCI Express feature Extended Tag in co= mplaince >=20 > - with the PCI Express Base specification Revision, a common value for a= ll the >=20 > - devices in the PCI hierarchy. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -AlignExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - if (PciExpressConfigurationTable) { >=20 > - // >=20 > - // align the Extended Tag value to a common value among all the devi= ces >=20 > - // >=20 > - PciDevice->SetupExtTag =3D MIN ( >=20 > - PciDevice->SetupExtTag, >=20 > - PciExpressConfigurationTable->ExtendedTag >=20 > - ); >=20 > - } >=20 > - >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "ExtTag: %d,", >=20 > - PciDevice->SetupExtTag >=20 > - )); >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Program the PCI Device Control 2 register for 10b Extended Tag value, = or the >=20 > - Device Control register for 5b/8b Extended Tag value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_DEVICE_CONTROL DevCtl; >=20 > - PCI_REG_PCIE_DEVICE_CONTROL2 DevCtl2; >=20 > - UINT32 Offset; >=20 > - UINT32 Offset2; >=20 > - BOOLEAN OverrideDevCtl; >=20 > - BOOLEAN OverrideDevCtl2; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - // >=20 > - // read the Device Control register for the Extended Tag Field Enable >=20 > - // >=20 > - DevCtl.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &DevCtl.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - OverrideDevCtl =3D FALSE; >=20 > - // >=20 > - // read the Device COntrol 2 register for the 10-Bit Tag Requester Ena= ble >=20 > - // >=20 > - DevCtl2.Uint16 =3D 0; >=20 > - Offset2 =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset2, >=20 > - 1, >=20 > - &DevCtl2.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - OverrideDevCtl2 =3D FALSE; >=20 > - >=20 > - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT) { >=20 > - if (DevCtl.Bits.ExtendedTagField) { >=20 > - DevCtl.Bits.ExtendedTagField =3D 0; >=20 > - OverrideDevCtl =3D TRUE; >=20 > - } >=20 > - >=20 > - if (DevCtl2.Bits.TenBitTagRequesterEnable) { >=20 > - DevCtl2.Bits.TenBitTagRequesterEnable =3D 0; >=20 > - OverrideDevCtl2 =3D TRUE; >=20 > - } >=20 > - } >=20 > - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT) { >=20 > - if (!DevCtl.Bits.ExtendedTagField) { >=20 > - DevCtl.Bits.ExtendedTagField =3D 1; >=20 > - OverrideDevCtl =3D TRUE; >=20 > - } >=20 > - if (DevCtl2.Bits.TenBitTagRequesterEnable) { >=20 > - DevCtl2.Bits.TenBitTagRequesterEnable =3D 0; >=20 > - OverrideDevCtl2 =3D TRUE; >=20 > - } >=20 > - } >=20 > - if (PciDevice->SetupExtTag =3D=3D EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT) = { >=20 > - if (!DevCtl2.Bits.TenBitTagRequesterEnable) { >=20 > - DevCtl2.Bits.TenBitTagRequesterEnable =3D 1; >=20 > - OverrideDevCtl2 =3D TRUE; >=20 > - } >=20 > - } >=20 > - >=20 > - if (OverrideDevCtl) { >=20 > - >=20 > - DEBUG (( DEBUG_INFO, "ExtTag=3D%d,", DevCtl.Bits.ExtendedTagField)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &DevCtl.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl.Uint16 =3D = DevCtl.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "no ExtTag (%d),", DevCtl.Bits.ExtendedTagField= )); >=20 > - } >=20 > - >=20 > - if (OverrideDevCtl2) { >=20 > - >=20 > - DEBUG (( DEBUG_INFO, "10bExtTag=3D%d,", DevCtl2.Bits.TenBitTagReques= terEnable)); >=20 > - >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset2, >=20 > - 1, >=20 > - &DevCtl2.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR(Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.DeviceControl2.Uint16 =3D= DevCtl2.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset2); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( DEBUG_INFO, "no 10bExtTag (%d),", DevCtl2.Bits.TenBitTagReq= uesterEnable)); >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Set the ASPM device policy as per the device's link capability. >=20 > -**/ >=20 > -UINT8 >=20 > -SetAspmPolicy ( >=20 > - IN UINT8 PciExpressLinkCapAspm >=20 > - ) >=20 > -{ >=20 > - switch (PciExpressLinkCapAspm) { >=20 > - case 0: >=20 > - // >=20 > - // cannot support ASPM state, disable >=20 > - // >=20 > - return EFI_PCI_EXPRESS_ASPM_DISABLE; >=20 > - case 1: >=20 > - // >=20 > - // supports only ASPM L0s state >=20 > - // >=20 > - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT; >=20 > - case 2: >=20 > - // >=20 > - // supports only ASPM L1 state >=20 > - // >=20 > - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT; >=20 > - case 3: >=20 > - // >=20 > - // supports both L0s and L1 ASPM states >=20 > - // >=20 > - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT; >=20 > - } >=20 > - return EFI_PCI_EXPRESS_ASPM_DISABLE; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature ASPM as per the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_LINK_CAPABILITY PciExLinkCap; >=20 > - PCI_REG_PCIE_DEVICE_CAPABILITY PciExpressDeviceCapability; >=20 > - BOOLEAN AlignAspmPolicy; >=20 > - >=20 > - PciExLinkCap.Uint32 =3D PciDevice->PciExpressCapabilityStructure.LinkC= apability.Uint32; >=20 > - PciExpressDeviceCapability.Uint32 =3D PciDevice->PciExpressCapabilityS= tructure.DeviceCapability.Uint32; >=20 > - // >=20 > - // ASPM support is only applicable to root bridge and its child device= s. Not >=20 > - // applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - PciExpressConfigurationTable->L0sExitLatency =3D MAX ( >=20 > - PciExpressConfigurationTable->L0sExitLatency, >=20 > - (UINT8)PciExLinkCap.Bits.L0sExitLatency >=20 > - ); >=20 > - PciExpressConfigurationTable->L1ExitLatency =3D MAX ( >=20 > - PciExpressConfigurationTable->L1ExitLatency, >=20 > - (UINT8)PciExLinkCap.Bits.L1ExitLatency >=20 > - ); >=20 > - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_AUTO) { >=20 > - // >=20 > - // set the ASPM support as per device's link capability >=20 > - // >=20 > - PciDevice->SetupAspm =3D SetAspmPolicy ((UINT8)PciExLinkCap.Bits.A= spm); >=20 > - } else { >=20 > - // >=20 > - // Check the ASPM device policy is applicable to the link capabili= ty. >=20 > - // In case of invalid device policy, there are 2 options: >=20 > - // (1) ASPM disable -> platform request rightly denied, and no ASP= M >=20 > - // (2) set as per the device capability -> platform request rightl= y denied, >=20 > - // but still set applicable power management >=20 > - // this implementation shall take option 2 to overule invalid plat= form request >=20 > - // and go with applicable policy as per device capability >=20 > - // >=20 > - switch (SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm)) { >=20 > - case EFI_PCI_EXPRESS_ASPM_DISABLE: >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_DISABLE; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT: >=20 > - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_L0s_SUPPO= RT) { >=20 > - // >=20 > - // not applicable, set as per device's link capability >=20 > - // >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_L1_SUPPORT; >=20 > - } >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT: >=20 > - if (PciDevice->SetupAspm =3D=3D EFI_PCI_EXPRESS_ASPM_L1_SUPPOR= T) { >=20 > - // >=20 > - // not applicable, set as per device's link capability >=20 > - // >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT; >=20 > - } >=20 > - break; >=20 > - } >=20 > - } >=20 > - // >=20 > - // set the ASPM policy to minimum state among all the devices links >=20 > - // >=20 > - PciExpressConfigurationTable->AspmSupport =3D MIN ( >=20 > - PciExpressConfiguratio= nTable->AspmSupport, >=20 > - PciDevice->SetupAspm >=20 > - ); >=20 > - // >=20 > - // check the common ASPM value applicable as per this device capabil= ity, if >=20 > - // not applicable disable the ASPM for all the devices >=20 > - // >=20 > - if ( >=20 > - (PciExpressConfigurationTable->AspmSupport =3D=3D EFI_PCI_EXPRESS_= ASPM_L0s_SUPPORT >=20 > - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) =3D=3D EFI_PCI_= EXPRESS_ASPM_L1_SUPPORT) >=20 > - || >=20 > - (PciExpressConfigurationTable->AspmSupport =3D=3D EFI_PCI_EXPRESS_= ASPM_L1_SUPPORT >=20 > - && SetAspmPolicy ((UINT8)PciExLinkCap.Bits.Aspm) =3D=3D EFI_PCI_= EXPRESS_ASPM_L0s_SUPPORT) >=20 > - ) { >=20 > - // >=20 > - // disable the ASPM >=20 > - // >=20 > - PciExpressConfigurationTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM= _DISABLE; >=20 > - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport= ; >=20 > - } >=20 > - >=20 > - if (PciExpressConfigurationTable->AspmSupport !=3D EFI_PCI_EXPRESS_A= SPM_DISABLE) { >=20 > - // >=20 > - // in case of ASPM policy is not to disable the ASPM support, chec= k other >=20 > - // condition of EP device L0s/L1 acceptance latency with the L0s/L= 1 exit >=20 > - // latencies comprising from this endpoint all the way up to root = complex >=20 > - // root port, to determine whether the ASPM L0s/L1 entry can be us= ed with >=20 > - // no loss of performance >=20 > - // >=20 > - if (!IS_PCI_BRIDGE (&PciDevice->Pci)) { >=20 > - >=20 > - switch (PciExpressConfigurationTable->AspmSupport) { >=20 > - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT: >=20 > - if ( >=20 > - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLat= ency >=3D PciExpressConfigurationTable->L0sExitLatency >=20 > - && PciExpressDeviceCapability.Bits.EndpointL1AcceptableL= atency >=3D PciExpressConfigurationTable- > >L1ExitLatency >=20 > - ) { >=20 > - // >=20 > - // both the L0s & L1 acceptance of this endpoint device is= greater >=20 > - // than or equal to all of the comprised L0s & L1 exit lat= encies >=20 > - // thus good to set the ASPM to L0s & L1 state >=20 > - // >=20 > - AlignAspmPolicy =3D TRUE; >=20 > - } else { >=20 > - // >=20 > - // in case the EP device L0s and L1 Acceptance latency doe= s not match >=20 > - // with the comprised L0s & L1 exit latencies than disable= the ASPM >=20 > - // state >=20 > - // >=20 > - AlignAspmPolicy =3D FALSE; >=20 > - } >=20 > - break; >=20 > - >=20 > - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT: >=20 > - if ( >=20 > - PciExpressDeviceCapability.Bits.EndpointL1AcceptableLate= ncy >=3D PciExpressConfigurationTable->L1ExitLatency >=20 > - ) { >=20 > - // >=20 > - // the endpoint device L1 acceptance latency meets the all= the >=20 > - // comprised L1 exit latencies of all the devices from the= bridge >=20 > - // hence ASPM L1 is applicable state for the PCI tree >=20 > - // >=20 > - AlignAspmPolicy =3D TRUE; >=20 > - } else { >=20 > - // >=20 > - // in case the EP device L1 Acceptance latency does not ma= tch >=20 > - // with the comprised L1 exit latencies than disable the A= SPM >=20 > - // state >=20 > - // >=20 > - AlignAspmPolicy =3D FALSE; >=20 > - } >=20 > - break; >=20 > - >=20 > - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT: >=20 > - if ( >=20 > - PciExpressDeviceCapability.Bits.EndpointL0sAcceptableLat= ency >=3D PciExpressConfigurationTable->L0sExitLatency >=20 > - ) { >=20 > - // >=20 > - // the endpoint device L0s acceptance latency meets the al= l the >=20 > - // comprised L0s exit latencies of all the devices from th= e bridge >=20 > - // hence ASPM L0s is applicable state for the PCI tree >=20 > - // >=20 > - AlignAspmPolicy =3D TRUE; >=20 > - } else { >=20 > - // >=20 > - // in case the EP device L0s Acceptance latency does not m= atch >=20 > - // with the comprised L0s exit latencies than disable the = ASPM >=20 > - // state >=20 > - // >=20 > - AlignAspmPolicy =3D FALSE; >=20 > - } >=20 > - break; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // align the bridge with the global common ASPM value >=20 > - // >=20 > - AlignAspmPolicy =3D TRUE; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // ASPM is disabled for all the devices >=20 > - // >=20 > - AlignAspmPolicy =3D FALSE; >=20 > - } >=20 > - >=20 > - if (AlignAspmPolicy) { >=20 > - // >=20 > - // reset the device's ASPM policy to common minimum value >=20 > - // >=20 > - if (PciDevice->SetupAspm !=3D PciExpressConfigurationTable->AspmSu= pport) { >=20 > - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSuppo= rt; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // disable the ASPM >=20 > - // >=20 > - PciExpressConfigurationTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM= _DISABLE; >=20 > - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport= ; >=20 > - } >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Aspm: %d [cap:%d],", >=20 > - PciDevice->SetupAspm, >=20 > - (PciExLinkCap.Bits.Aspm + 1) >=20 > - )); >=20 > - } >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetu= pPhase >=20 > -**/ >=20 > -EFI_STATUS >=20 > -AlignAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // ASPM support is only applicable to root bridge and its child device= s. Not >=20 > - // applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - // >=20 > - // reset the device's ASPM policy to common minimum ASPM value >=20 > - // >=20 > - if (PciDevice->SetupAspm !=3D PciExpressConfigurationTable->AspmSupp= ort) { >=20 > - PciDevice->SetupAspm =3D PciExpressConfigurationTable->AspmSupport= ; >=20 > - } >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Aspm: %d,", >=20 > - PciDevice->SetupAspm >=20 > - )); >=20 > - } >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > - >=20 > -/** >=20 > - Get the ASPM value from the ASPM device policy. >=20 > -**/ >=20 > -UINT8 >=20 > -GetAspmValue ( >=20 > - IN UINT8 AspmPolicy >=20 > - ) >=20 > -{ >=20 > - switch (AspmPolicy) { >=20 > - case EFI_PCI_EXPRESS_ASPM_DISABLE: >=20 > - // >=20 > - // ASPM disable >=20 > - // >=20 > - return 0; >=20 > - case EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT: >=20 > - // >=20 > - // ASPM L0s state >=20 > - // >=20 > - return 1; >=20 > - case EFI_PCI_EXPRESS_ASPM_L1_SUPPORT: >=20 > - // >=20 > - // ASPM L1 state >=20 > - // >=20 > - return 2; >=20 > - case EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT: >=20 > - // >=20 > - // L0s and L1 ASPM states >=20 > - // >=20 > - return 3; >=20 > - } >=20 > - return 0; >=20 > -} >=20 > - >=20 > -/** >=20 > - Program the PCIe Link Control register ASPM Control field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_LINK_CONTROL LinkCtl; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - UINT8 AspmValue; >=20 > - >=20 > - // >=20 > - // ASPM support is only applicable to root bridge and its child device= s. Not >=20 > - // applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (!PciExFeatureConfiguration) { >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // read the link Control register for the ASPM Control >=20 > - // >=20 > - LinkCtl.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkCtl.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - AspmValue =3D GetAspmValue (PciDevice->SetupAspm); >=20 > - if (AspmValue !=3D LinkCtl.Bits.AspmControl) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Aspm: %d,", >=20 > - AspmValue >=20 > - )); >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkCtl.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR (Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Li= nkCtl.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - return Status; >=20 > - } >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "No Aspm (%d),", >=20 > - AspmValue >=20 > - )); >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature Common Clock configu= ration >=20 > - as per the device-specific platform policy, as well as in complaince w= ith the >=20 > - PCI Express Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupCommonClkCfg ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_LINK_STATUS LinkSts; >=20 > - >=20 > - LinkSts.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkStatus= .Uint16; >=20 > - >=20 > - // >=20 > - // Common Clock Configuration is only applicable to root bridge and it= s child >=20 > - // devices. Not applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (PciExpressConfigurationTable) { >=20 > - if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_AUTO) { >=20 > - // >=20 > - // as per the PCI Express Base Specification, the link status regi= ster >=20 > - // slot clock configuration of the opposing side of link devices i= ndicate >=20 > - // the clock configuration properly; hence rely on this data to co= nfigure >=20 > - // the link's clock configuration >=20 > - // >=20 > - if (LinkSts.Bits.SlotClockConfiguration) { >=20 > - PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE; >=20 > - } else { >=20 > - PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE= ; >=20 > - } >=20 > - } else if (PciDevice->SetupCcc =3D=3D EFI_PCI_EXPRESS_CLK_CFG_ASYNCH= ) { >=20 > - // >=20 > - // platform override to any device shall change for other device o= n the >=20 > - // link, the clock configuration has to be maintained common acros= s all >=20 > - // the devices >=20 > - // >=20 > - PciExpressConfigurationTable->CommonClockConfiguration =3D FALSE; >=20 > - } else { >=20 > - PciExpressConfigurationTable->CommonClockConfiguration =3D TRUE; >=20 > - } >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Program the PCIe Link Control register Coomon Clock Configuration fiel= d; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramCcc ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_LINK_CONTROL LinkCtl; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - // >=20 > - // Common Clock Configuration is only applicable to root bridge and it= s child >=20 > - // devices. Not applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (!PciExFeatureConfiguration) { >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // read the link Control register for the ASPM Control >=20 > - // >=20 > - LinkCtl.Uint16 =3D 0; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl); >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkCtl.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - >=20 > - // >=20 > - // in case Common Clock Configuration is required to be programmed in = the >=20 > - // downstream ports from the root bridge devices in the heirarchy >=20 > - // >=20 > - if (PciExFeatureConfiguration->CommonClockConfiguration =3D=3D TRUE) { >=20 > - if (LinkCtl.Bits.CommonClockConfiguration =3D=3D 0) { >=20 > - LinkCtl.Bits.CommonClockConfiguration =3D 1; >=20 > - // >=20 > - // current clock mode does not match hence retrain of the link at = bridge device >=20 > - // is required >=20 > - // >=20 > - PciExFeatureConfiguration->LinkReTrain =3D TRUE; >=20 > - } >=20 > - } else { >=20 > - // >=20 > - // in case the opposing devices of the PCI link have different refer= ence clock >=20 > - // set the link control register CCC field accordingly >=20 > - // >=20 > - if (LinkCtl.Bits.CommonClockConfiguration) { >=20 > - LinkCtl.Bits.CommonClockConfiguration =3D 0; >=20 > - // >=20 > - // current clock mode does not match hence retrain of the link at = bridge device >=20 > - // is required >=20 > - // >=20 > - PciExFeatureConfiguration->LinkReTrain =3D TRUE; >=20 > - } >=20 > - } >=20 > - // >=20 > - // use the retrain flag as a sigm to also update the CCC of the link r= egister >=20 > - // >=20 > - if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "CCC: %d,", >=20 > - LinkCtl.Bits.CommonClockConfiguration >=20 > - )); >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the writ= e operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkCtl.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR (Status)) { >=20 > - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Li= nkCtl.Uint16; >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNumber= , PciDevice->FunctionNumber, Offset); >=20 > - return Status; >=20 > - } >=20 > - } else { >=20 > - PciDevice->PciExpressCapabilityStructure.LinkControl.Uint16 =3D Link= Ctl.Uint16; >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "No CCC (%d),", >=20 > - LinkCtl.Bits.CommonClockConfiguration >=20 > - )); >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Second phase of programming for Common Clock COnfiguration, conditoona= lly done >=20 > - only on the downstream ports (bridge devices only). >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -EnforceCcc ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration >=20 > - ) >=20 > -{ >=20 > - PCI_REG_PCIE_LINK_CONTROL LinkCtl; >=20 > - PCI_REG_PCIE_LINK_STATUS LinkSts; >=20 > - PCI_REG_PCIE_CAPABILITY PciExCap; >=20 > - UINT32 Offset; >=20 > - EFI_STATUS Status; >=20 > - EFI_TPL OldTpl; >=20 > - >=20 > - // >=20 > - // Common Clock Configuration is only applicable to root bridge and it= s child >=20 > - // devices. Not applicable to empty bridge devices or RCiEP devices >=20 > - // >=20 > - if (!PciExFeatureConfiguration) { >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - PciExCap.Uint16 =3D PciDevice->PciExpressCapabilityStructure.Capabilit= y.Uint16; >=20 > - LinkCtl.Uint16 =3D PciDevice->PciExpressCapabilityStructure.LinkContro= l.Uint16; >=20 > - >=20 > - // >=20 > - // retrain the bridge device (downstream ports including the root port= ) >=20 > - // >=20 > - if (PciExFeatureConfiguration->LinkReTrain =3D=3D TRUE) { >=20 > - if (IS_PCI_BRIDGE (&PciDevice->Pci)) { >=20 > - // >=20 > - // retrain of the PCI link happens for CCC change only on the down= stream >=20 > - // ports >=20 > - // >=20 > - if ( >=20 > - PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_ROOT_P= ORT >=20 > - || PciExCap.Bits.DevicePortType =3D=3D PCIE_DEVICE_PORT_TYPE_DOW= NSTREAM_PORT >=20 > - ) { >=20 > - LinkCtl.Bits.RetrainLink =3D 1; >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkControl); >=20 > - // >=20 > - // Raise TPL to high level to disable timer interrupt while the = write operation completes >=20 > - // >=20 > - OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); >=20 > - >=20 > - Status =3D PciDevice->PciIo.Pci.Write ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkCtl.Uint16 >=20 > - ); >=20 > - // >=20 > - // Restore TPL to its original level >=20 > - // >=20 > - gBS->RestoreTPL (OldTpl); >=20 > - >=20 > - if (!EFI_ERROR (Status)) { >=20 > - // >=20 > - // poll the link status register for the link retrain to be co= mplete >=20 > - // >=20 > - Offset =3D PciDevice->PciExpressCapabilityOffset + >=20 > - OFFSET_OF (PCI_CAPABILITY_PCIEXP, LinkSta= tus); >=20 > - do { >=20 > - Status =3D PciDevice->PciIo.Pci.Read ( >=20 > - &PciDevice->PciIo, >=20 > - EfiPciIoWidthUint16, >=20 > - Offset, >=20 > - 1, >=20 > - &LinkSts.Uint16 >=20 > - ); >=20 > - ASSERT (Status =3D=3D EFI_SUCCESS); >=20 > - } while (LinkSts.Bits.LinkTraining); >=20 > - } else { >=20 > - ReportPciWriteError (PciDevice->BusNumber, PciDevice->DeviceNu= mber, PciDevice->FunctionNumber, Offset); >=20 > - return Status; >=20 > - } >=20 > - } >=20 > - // >=20 > - // ignore the upstream bridge devices >=20 > - // >=20 > - } >=20 > - // >=20 > - // not applicable to endpoint devices >=20 > - // >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > deleted file mode 100644 > index 33df337..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciExpressFeatures.h > +++ /dev/null > @@ -1,399 +0,0 @@ > -/** @file >=20 > - PCI standard feature support functions implementation for PCI Bus modu= le.. >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > -#ifndef _EFI_PCI_EXPRESS_FEATURES_H_ >=20 > -#define _EFI_PCI_EXPRESS_FEATURES_H_ >=20 > - >=20 > -// >=20 > -// PCIe L0s Exit Latencies declarations >=20 > -// >=20 > -#define PCIE_LINK_CAPABILITY_L0S_EXIT_LATENCY_64NS 0 // less than 64n= s >=20 > - >=20 > -// >=20 > -// PCIe L1 Exit latencies declarations >=20 > -// >=20 > -#define PCIE_LINK_CAPABILITY_L1_EXIT_LATENCY_1US 0 // less than 1us >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature Max_Payload_Size as per= the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4, that aligns the value for the entire PCI hei= rarchy >=20 > - starting from its physical PCI Root port / Bridge device. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature Max_Pa= yload_Size >=20 > - is successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -EFI_STATUS >=20 > -CasMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register Max_Read_Req_Size register f= ield; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI controller. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramMaxPayloadSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > - >=20 > -EFI_STATUS >=20 > -ConditionalCasMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature Max_Read_Req_Size as pe= r the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4, that aligns the value for the entire PCI hei= rarchy >=20 > - starting from its physical PCI Root port / Bridge device. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciConfigPhase for the PCI feature configuratio= n phases: >=20 > - PciExpressFeatureSetupPhase & Pc= iExpressFeatureEntendedSetupPhase >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature Max_Re= ad_Req_Size >=20 > - is successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register Max_Read_Req_Size register f= ield; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI controller. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramMaxReadReqSize ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register Relax Order register field; = if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramRelaxOrder ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control register No-Snoop register field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramNoSnoop ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature Completion Timeout as p= er the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Base >=20 > - specification Revision 4. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciConfigPhase for the PCI feature configuratio= n phases: >=20 > - PciExpressFeatureSetupPhase & Pc= iExpressFeatureEntendedSetupPhase >=20 > - >=20 > - @retval EFI_SUCCESS processing of PCI feature CTO is= successful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupCompletionTimeout ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control2 register Completion Timeout range; i= f >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramCompletionTimeout ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - Routine to setup the AtomicOp Requester in the PCI device, verifies th= e routing >=20 > - support in the bridge devices, to be complaint as per the PCI Base spe= cification. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExFeatureConfiguration pointer to common configuration = table to >=20 > - initialize the PCI Express featu= re >=20 > - >=20 > - @retval EFI_SUCCESS bridge device routing capability= is successful. >=20 > - EFI_INVALID_PARAMETER input parameter is NULL >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupAtomicOpRoutingSupport ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfigurati= on >=20 > - ); >=20 > - >=20 > -/** >=20 > - Overrides the PCI Device Control 2 register AtomicOp Requester enable = field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramAtomicOp ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine which process the PCI feature LTR enable/disable as p= er the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -EFI_STATUS >=20 > -ReSetupLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Program the PCI Device Control 2 register LTR mechanism field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramLtr ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature Extended Tag as per = the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Additional routine to setup the PCI Express feature Extended Tag in co= mplaince >=20 > - with the PCI Express Base specification Revision, a common value for a= ll the >=20 > - devices in the PCI hierarchy. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -AlignExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Program the PCI Device Control 2 register for 10b Extended Tag value, = or the >=20 > - Device Control register for 5b/8b Extended Tag value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature ASPM as per the >=20 > - device-specific platform policy, as well as in complaince with the PCI= Express >=20 > - Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciFeaturesConfigurationTable pointer to PCI_EXPRESS_FEATURES_= CONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Setup of PCI Express feature ASPM in the PciExpressFeatureEntendedSetu= pPhase >=20 > -**/ >=20 > -EFI_STATUS >=20 > -AlignAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfiguratio= nTable >=20 > - ); >=20 > - >=20 > -/** >=20 > - Program the PCIe Link Control register ASPM Control field; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramAspm ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - The main routine to setup the PCI Express feature Common Clock configu= ration >=20 > - as per the device-specific platform policy, as well as in complaince w= ith the >=20 > - PCI Express Base specification Revision 5. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - @param PciExpressConfigurationTable pointer to PCI_EXPRESS_FEATURES_C= ONFIGURATION_TABLE >=20 > - >=20 > - @retval EFI_SUCCESS setup of PCI feature LTR is succ= essful. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -SetupCommonClkCfg ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressConfiguration= Table >=20 > - ); >=20 > - >=20 > -/** >=20 > - Program the PCIe Link Control register Coomon Clock Configuration fiel= d; if >=20 > - the hardware value is different than the intended value. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -ProgramCcc ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration >=20 > - ); >=20 > - >=20 > -/** >=20 > - Second phase of programming for Common Clock COnfiguration, conditoona= lly done >=20 > - only on the downstream ports (bridge devices only). >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE instance. >=20 > - >=20 > - @retval EFI_SUCCESS The data was read from or written to the= PCI device. >=20 > - @retval EFI_UNSUPPORTED The address range specified by Offset, W= idth, and Count is not >=20 > - valid for the PCI configuration header o= f the PCI controller. >=20 > - @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. >=20 > - >=20 > -**/ >=20 > -EFI_STATUS >=20 > -EnforceCcc ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeatureConfiguration >=20 > - ); >=20 > -#endif >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > deleted file mode 100644 > index 4d3641c..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c > +++ /dev/null > @@ -1,1019 +0,0 @@ > -/** @file >=20 > - PCI standard feature support functions implementation for PCI Bus modu= le.. >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > -#include "PciBus.h" >=20 > -#include "PciFeatureSupport.h" >=20 > -#include "PciExpressFeatures.h" >=20 > - >=20 > -/** >=20 > - Hold the current instance of Root Bridge IO protocol Handle >=20 > -**/ >=20 > -EFI_HANDLE mRootBridgeHandle; >=20 > - >=20 > -/** >=20 > - A gobal pointer to BRIDGE_DEVICE_NODE buffer to track all the primary = physical >=20 > - PCI Root Ports (PCI Controllers) for a given PCI Root Bridge instance = while >=20 > - enumerating to configure the PCI features >=20 > -**/ >=20 > -LIST_ENTRY mRootBridgeDeviceList; >=20 > - >=20 > -/** >=20 > - global list to indicate the supported PCI Express features of this driv= er, it >=20 > - is expected to be overridden based on the platform request >=20 > -**/ >=20 > -EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformPolicy = =3D { >=20 > - // >=20 > - // support for PCI Express feature - Max. Payload Size >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Max. Read Request Size >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Extended Tag >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Relax Order >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - No-Snoop >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - ASPM state >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Common Clock Configuration >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Extended Sync >=20 > - // >=20 > - FALSE, >=20 > - // >=20 > - // support for PCI Express feature - Atomic Op >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - LTR >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - PTM >=20 > - // >=20 > - FALSE, >=20 > - // >=20 > - // support for PCI Express feature - Completion Timeout >=20 > - // >=20 > - TRUE, >=20 > - // >=20 > - // support for PCI Express feature - Clock Power Management >=20 > - // >=20 > - FALSE, >=20 > - // >=20 > - // support for PCI Express feature - L1 PM Substates >=20 > - // >=20 > - FALSE >=20 > -}; >=20 > - >=20 > -// >=20 > -// indicates the driver has completed query to platform on the list of s= upported >=20 > -// PCI features to be configured >=20 > -// >=20 > -BOOLEAN mPciExpressGetPlatformPolicyComplete =3D FALSE; >=20 > - >=20 > -// >=20 > -// PCI Express feature initialization phase handle routines >=20 > -// >=20 > -PCI_EXPRESS_FEATURE_INITIALIZATION_POINT mPciExpressFeatureInitializati= onList[] =3D { >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressCcc, SetupCom= monClkCfg >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressCcc, ProgramC= cc >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressCcc, EnforceC= cc >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressAspm, SetupAsp= m >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressAspm, AlignAsp= m >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressAspm, ProgramA= spm >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressMps, SetupMax= PayloadSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressMps, CasMaxPa= yloadSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressMps, ProgramM= axPayloadSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressMrrs, SetupMax= ReadReqSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressMrrs, Conditio= nalCasMaxReadReqSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressMrrs, ProgramM= axReadReqSize >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressRelaxOrder, ProgramR= elaxOrder >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressNoSnoop, ProgramN= oSnoop >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressCto, SetupCom= pletionTimeout >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressCto, ProgramC= ompletionTimeout >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressAtomicOp, SetupAto= micOpRoutingSupport >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressAtomicOp, ProgramA= tomicOp >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressLtr, SetupLtr >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressLtr, ReSetupL= tr >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressLtr, ProgramL= tr >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureSetupPhase, PciExpressExtTag, SetupExt= Tag >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureEntendedSetupPhase, PciExpressExtTag, AlignExt= Tag >=20 > - }, >=20 > - { >=20 > - PciExpressFeatureProgramPhase, PciExpressExtTag, ProgramE= xtTag >=20 > - } >=20 > -}; >=20 > - >=20 > -/** >=20 > - Routine to serially dispatch the designated the PCI Express feature sp= ecific >=20 > - functions defined for each of the configuration phase. The order for e= ach phase >=20 > - would be based entirely on the table mPciExpressFeatureInitializationL= ist. >=20 > - >=20 > - @param PciDevice pointer to PCI_IO_DEVICE to id= entify device >=20 > - @param PciExFeatureConfigPhase input configuration phase >=20 > - @param PciExpressFeatureConfiguration used pointer to void to accomo= date any PCI >=20 > - Express feature specific data = type >=20 > - @retval EFI_STATUS output only from feature speci= fic function >=20 > - defined in the table mPciExpre= ssFeatureInitializationList >=20 > -**/ >=20 > -EFI_STATUS >=20 > -DispatchPciExpressInitializationFunctions ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExFeatureConfigPhase, >=20 > - IN VOID *PciExpressFeatureConfigur= ation >=20 > - ) >=20 > -{ >=20 > - UINTN idx; >=20 > - EFI_STATUS Status; >=20 > - UINT8 *PciExpressPolicy; >=20 > - >=20 > - for ( >=20 > - idx =3D 0, PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy >=20 > - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PC= I_EXPRESS_FEATURE_INITIALIZATION_POINT) >=20 > - ; idx++ >=20 > - ){ >=20 > - if ( >=20 > - // >=20 > - // match the configuration phase >=20 > - // >=20 > - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfi= gurationPhase =3D=3D PciExFeatureConfigPhase >=20 > - // >=20 > - // check whether the PCI Express features is enabled >=20 > - // >=20 > - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].Pc= iExpressFeatureId] =3D=3D TRUE >=20 > - ) { >=20 > - Status =3D mPciExpressFeatureInitializationList[idx].PciExpressFe= atureConfigurationRoutine ( >=20 > - PciDevice, >=20 > - PciExpressFe= atureConfiguration >=20 > - ); >=20 > - } >=20 > - } >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Main routine to indicate platform selection of any of the other PCI fe= atures >=20 > - to be configured by this driver >=20 > - >=20 > - @retval TRUE platform has selected the other PCI features to be con= figured >=20 > - FALSE platform has not selected any of the other PCI feature= s >=20 > -**/ >=20 > -BOOLEAN >=20 > -CheckPciExpressFeatureList ( >=20 > - ) >=20 > -{ >=20 > - UINTN length; >=20 > - UINT8 *list; >=20 > - >=20 > - for ( >=20 > - length =3D 0, list =3D (UINT8*)&mPciExpressPlatformPolicy >=20 > - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY) >=20 > - ; length++ >=20 > - ) { >=20 > - if (list[length]) { >=20 > - return TRUE; >=20 > - } >=20 > - } >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - helper routine to wipe out the global PCI Express feature list >=20 > -**/ >=20 > -VOID >=20 > -NegatePciExpressFeatureList ( >=20 > - ) >=20 > -{ >=20 > - UINTN length; >=20 > - UINT8 *list; >=20 > - >=20 > - for ( >=20 > - length =3D 0, list =3D (UINT8*)&mPciExpressPlatformPolicy >=20 > - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY) >=20 > - ; length++ >=20 > - ) { >=20 > - if (list[length]) { >=20 > - list[length] =3D FALSE; >=20 > - } >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Main routine to indicate whether the PCI Express feature initializatio= n is >=20 > - required or not >=20 > - >=20 > - @retval TRUE PCI Express feature initialization required >=20 > - FALSE PCI Express feature not required >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsPciExpressFeatureConfigurationRequired ( >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - >=20 > - if (mPciExpressGetPlatformPolicyComplete) { >=20 > - return CheckPciExpressFeatureList (); >=20 > - } >=20 > - // >=20 > - // initialize the PCI Express feature data members >=20 > - // >=20 > - InitializeListHead (&mRootBridgeDeviceList); >=20 > - // >=20 > - // check the platform to configure the PCI Express features >=20 > - // >=20 > - mPciExpressGetPlatformPolicyComplete =3D TRUE; >=20 > - >=20 > - Status =3D PciExpressPlatformGetPolicy (); >=20 > - if (EFI_ERROR (Status)) { >=20 > - // >=20 > - // fail to obtain the PCI Express feature configuration from platfor= m, >=20 > - // negate the list to avoid any unwanted configuration >=20 > - // >=20 > - NegatePciExpressFeatureList (); >=20 > - return FALSE; >=20 > - } >=20 > - // >=20 > - // PCI Express feature configuration list is ready from platform >=20 > - // >=20 > - return TRUE; >=20 > -} >=20 > - >=20 > - >=20 > -/** >=20 > - Indicates whether the set of PCI Express features selected by platform= requires >=20 > - extended setup, that has additional resources that would be allocated = to align >=20 > - all the devices in the PCI tree, and free the resources later. >=20 > - >=20 > - @retval TRUE PCI Express feature requires extended setup >=20 > - FALSE PCI Express feature does not require extended setup >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsPciExpressFeatureExtendedSetupRequired ( >=20 > - ) >=20 > -{ >=20 > - UINTN idx; >=20 > - UINT8 *PciExpressPolicy; >=20 > - // >=20 > - // return TRUE only for those features which are required to be aligne= d with >=20 > - // common values among all the devices in the PCI tree >=20 > - // >=20 > - for ( >=20 > - idx =3D 0, PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy >=20 > - ; idx < sizeof (mPciExpressFeatureInitializationList) / sizeof (PC= I_EXPRESS_FEATURE_INITIALIZATION_POINT) >=20 > - ; idx++ >=20 > - ){ >=20 > - if ( >=20 > - // >=20 > - // match the configuration phase to extended setup phase >=20 > - // >=20 > - mPciExpressFeatureInitializationList[idx].PciExpressFeatureConfi= gurationPhase =3D=3D > PciExpressFeatureEntendedSetupPhase >=20 > - // >=20 > - // check whether the PCI Express features is enabled >=20 > - // >=20 > - && PciExpressPolicy[mPciExpressFeatureInitializationList[idx].Pc= iExpressFeatureId] =3D=3D TRUE >=20 > - ) { >=20 > - return TRUE; >=20 > - } else if ( >=20 > - // >=20 > - // the PCI Express feature does not require extended setup phase= but it >=20 > - // does require global flag to track the AtomicOpRouting caoabil= ity to >=20 > - // be tracked for all its bridge devices >=20 > - // >=20 > - idx =3D=3D PciExpressAtomicOp >=20 > - && PciExpressPolicy[idx] =3D=3D TRUE >=20 > - ) { >=20 > - return TRUE; >=20 > - } >=20 > - } >=20 > - >=20 > - return FALSE; >=20 > -} >=20 > - >=20 > -/** >=20 > - Helper routine to determine the existence of previously enumerated PCI = device >=20 > - >=20 > - @retval TRUE PCI device exist >=20 > - FALSE does not exist >=20 > -**/ >=20 > -BOOLEAN >=20 > -DeviceExist ( >=20 > - PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - EFI_PCI_IO_PROTOCOL *PciIoProtocol =3D &PciDevice->PciIo; >=20 > - UINT16 VendorId =3D 0xFFFF; >=20 > - >=20 > - PciIoProtocol->Pci.Read ( >=20 > - PciIoProtocol, >=20 > - EfiPciIoWidthUint16, >=20 > - PCI_VENDOR_ID_OFFSET, >=20 > - 1, >=20 > - &VendorId >=20 > - ); >=20 > - if (VendorId =3D=3D 0 || VendorId =3D=3D 0xFFFF) { >=20 > - return FALSE; >=20 > - } else { >=20 > - return TRUE; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Free up memory alloted for the primary physical PCI Root ports of the = PCI Root >=20 > - Bridge instance. Free up all the nodes of type BRIDGE_DEVICE_NODE. >=20 > -**/ >=20 > -VOID >=20 > -DestroyRootBridgeDeviceNodes () >=20 > -{ >=20 > - LIST_ENTRY *Link; >=20 > - BRIDGE_DEVICE_NODE *Temp; >=20 > - >=20 > - Link =3D mRootBridgeDeviceList.ForwardLink; >=20 > - while (Link !=3D NULL && Link !=3D &mRootBridgeDeviceList) { >=20 > - Temp =3D ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link); >=20 > - Link =3D RemoveEntryList (Link); >=20 > - FreePool (Temp->PciExFeaturesConfigurationTable); >=20 > - FreePool (Temp); >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Main routine to determine the child PCI devices of a PCI bridge device >=20 > - and group them under a common internal PCI features Configuration tabl= e. >=20 > - >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE= . >=20 > - @param PciFeaturesConfigTable A pointer to a pointer to the >=20 > - PCI_EXPRESS_FEATURES_CONFIGURA= TION_TABLE. >=20 > - Returns NULL in case of RCiEP = or the PCI >=20 > - device does match with any of = the physical >=20 > - Root ports, or it does not bel= ong to any >=20 > - Root port's PCI bus range (not= a child) >=20 > - >=20 > - @retval EFI_SUCCESS able to determine the PCI feat= ure >=20 > - configuration table. For RCiEP= since >=20 > - since it is not prepared. >=20 > - EFI_DEVICE_ERROR the PCI device has invalid EFI= device >=20 > - path >=20 > -**/ >=20 > -EFI_STATUS >=20 > -GetPciExpressFeaturesConfigurationTable ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - OUT PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE **PciFeaturesConfigTable >=20 > - ) >=20 > -{ >=20 > - LIST_ENTRY *Link; >=20 > - BRIDGE_DEVICE_NODE *Temp; >=20 > - BOOLEAN NodeMatch; >=20 > - EFI_DEVICE_PATH_PROTOCOL *RootPortPath; >=20 > - EFI_DEVICE_PATH_PROTOCOL *PciDevicePath; >=20 > - >=20 > - if (IsListEmpty (&mRootBridgeDeviceList)) { >=20 > - // >=20 > - // no populated PCI primary root ports to parse and match the PCI fe= atures >=20 > - // configuration table >=20 > - // >=20 > - *PciFeaturesConfigTable =3D NULL; >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // The PCI features configuration table is not built for RCiEP, return= NULL >=20 > - // >=20 > - if (PciDevice->PciExpressCapabilityStructure.Capability.Bits.DevicePor= tType =3D=3D \ >=20 > - PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) { >=20 > - *PciFeaturesConfigTable =3D NULL; >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - if (IsDevicePathEnd (PciDevice->DevicePath)){ >=20 > - // >=20 > - // the given PCI device does not have a valid device path >=20 > - // >=20 > - *PciFeaturesConfigTable =3D NULL; >=20 > - return EFI_DEVICE_ERROR; >=20 > - } >=20 > - >=20 > - >=20 > - Link =3D mRootBridgeDeviceList.ForwardLink; >=20 > - do { >=20 > - Temp =3D ROOT_BRIDGE_DEVICE_NODE_FROM_LINK (Link); >=20 > - RootPortPath =3D Temp->RootBridgeDevicePath; >=20 > - PciDevicePath =3D PciDevice->DevicePath; >=20 > - NodeMatch =3D FALSE; >=20 > - // >=20 > - // match the device path from the list of primary Root Ports with th= e given >=20 > - // device; the initial nodes matching in sequence indicate that the = given PCI >=20 > - // device belongs to that PCI tree from the root port >=20 > - // >=20 > - if (IsDevicePathEnd (RootPortPath)) { >=20 > - // >=20 > - // critical error as no device path available in root >=20 > - // >=20 > - *PciFeaturesConfigTable =3D NULL; >=20 > - return EFI_DEVICE_ERROR; >=20 > - } >=20 > - >=20 > - if (EfiCompareDevicePath (RootPortPath, PciDevicePath)) { >=20 > - // >=20 > - // the given PCI device is the primary root port itself >=20 > - // >=20 > - *PciFeaturesConfigTable =3D Temp->PciExFeaturesConfigurationTable; >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - // >=20 > - // check this PCI device belongs to the primary root port of the roo= t bridge >=20 > - // any child PCI device will have the same initial device path nodes= as >=20 > - // its parent root port >=20 > - // >=20 > - while (!IsDevicePathEnd (RootPortPath)){ >=20 > - >=20 > - if (DevicePathNodeLength (RootPortPath) !=3D DevicePathNodeLength = (PciDevicePath)) { >=20 > - // >=20 > - // break to check the next primary root port nodes as does not m= atch >=20 > - // >=20 > - NodeMatch =3D FALSE; >=20 > - break; >=20 > - } >=20 > - if (CompareMem (RootPortPath, PciDevicePath, DevicePathNodeLength = (RootPortPath)) !=3D 0) { >=20 > - // >=20 > - // node does not match, break to check next node >=20 > - // >=20 > - NodeMatch =3D FALSE; >=20 > - break; >=20 > - } >=20 > - NodeMatch =3D TRUE; >=20 > - // >=20 > - // advance to next node >=20 > - // >=20 > - RootPortPath =3D NextDevicePathNode (RootPortPath); >=20 > - PciDevicePath =3D NextDevicePathNode (PciDevicePath); >=20 > - } >=20 > - >=20 > - if (NodeMatch =3D=3D TRUE) { >=20 > - // >=20 > - // device belongs to primary root port, return its PCI feature con= figuration >=20 > - // table >=20 > - // >=20 > - *PciFeaturesConfigTable =3D Temp->PciExFeaturesConfigurationTable; >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - >=20 > - // >=20 > - // advance to next Root port node >=20 > - // >=20 > - Link =3D Link->ForwardLink; >=20 > - } while (Link !=3D &mRootBridgeDeviceList && Link !=3D NULL); >=20 > - // >=20 > - // the PCI device must be RCiEP, does not belong to any primary root p= ort >=20 > - // >=20 > - *PciFeaturesConfigTable =3D NULL; >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - helper routine to dump the PCIe Device Port Type >=20 > -**/ >=20 > -VOID >=20 > -DumpDevicePortType ( >=20 > - IN UINT8 DevicePortType >=20 > - ) >=20 > -{ >=20 > - switch (DevicePortType){ >=20 > - case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT: >=20 > - DEBUG (( DEBUG_INFO, "PCIe endpoint found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT: >=20 > - DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_ROOT_PORT: >=20 > - DEBUG (( DEBUG_INFO, "PCIe Root Port found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT: >=20 > - DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT: >=20 > - DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE: >=20 > - DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE: >=20 > - DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT: >=20 > - DEBUG (( DEBUG_INFO, "RCiEP found\n")); >=20 > - break; >=20 > - case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR: >=20 > - DEBUG (( DEBUG_INFO, "RC Event Collector found\n")); >=20 > - break; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Setup each PCI device as per the pltaform's device-specific policy, i= n accordance >=20 > - with PCI Express Base specification. >=20 > - >=20 > - @param RootBridge A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS processing each PCI feature as per polic= y defined >=20 > - was successful. >=20 > - **/ >=20 > -EFI_STATUS >=20 > -SetupDevicePciExpressFeatures ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - PCI_REG_PCIE_CAPABILITY PcieCap; >=20 > - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExpressFeaturesConfigTab= le; >=20 > - >=20 > - PciExpressFeaturesConfigTable =3D NULL; >=20 > - Status =3D GetPciExpressFeaturesConfigurationTable (PciDevice, &PciExp= ressFeaturesConfigTable); >=20 > - >=20 > - if (PciConfigPhase =3D=3D PciExpressFeatureSetupPhase) { >=20 > - DEBUG_CODE ( >=20 > - if (EFI_ERROR( Status)) { >=20 > - DEBUG (( >=20 > - DEBUG_WARN, >=20 > - "[Cfg group: 0 {error in dev path}]" >=20 > - )); >=20 > - } else if (PciExpressFeaturesConfigTable =3D=3D NULL) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "[Cfg group: 0]" >=20 > - )); >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "[Cfg group: %d]", >=20 > - PciExpressFeaturesConfigTable->ID >=20 > - )); >=20 > - } >=20 > - PcieCap.Uint16 =3D PciDevice->PciExpressCapabilityStructure.Capabi= lity.Uint16; >=20 > - DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType); >=20 > - ); >=20 > - >=20 > - // >=20 > - // get the device-specific platform policy for the PCI Express featu= res >=20 > - // >=20 > - Status =3D PciExpressPlatformGetDevicePolicy (PciDevice); >=20 > - if (EFI_ERROR(Status)) { >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "Error in obtaining PCI device policy!!!\n" >=20 > - )); >=20 > - } >=20 > - } >=20 > - >=20 > - DEBUG ((DEBUG_INFO, "[")); >=20 > - >=20 > - Status =3D DispatchPciExpressInitializationFunctions ( >=20 > - PciDevice, >=20 > - PciConfigPhase, >=20 > - PciExpressFeaturesConfigTable >=20 > - ); >=20 > - >=20 > - DEBUG ((DEBUG_INFO, "]\n")); >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Create and append a node of type BRIDGE_DEVICE_NODE in the list for th= e primary >=20 > - Root Port so that all its child PCI devices can be identified against = the PCI >=20 > - features configuration table group ID, of type PCI_EXPRESS_FEATURES_CO= NFIGURATION_TABLE. >=20 > - >=20 > - @param BridgePort A pointer to the PCI_IO_DEVICE >=20 > - @param PortNumber A UINTN value to identify the PCI feature configu= ration >=20 > - table group >=20 > - >=20 > - @retval EFI_SUCCESS success in adding a node of BRIDGE_DEVIC= E_NODE >=20 > - to the list >=20 > - EFI_OUT_OF_RESOURCES unable to get memory for creating the no= de >=20 > -**/ >=20 > -EFI_STATUS >=20 > -CreatePciRootBridgeDeviceNode ( >=20 > - IN PCI_IO_DEVICE *BridgePort, >=20 > - IN UINTN PortNumber >=20 > - ) >=20 > -{ >=20 > - BRIDGE_DEVICE_NODE *RootBridgeNode =3D NULL; >=20 > - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciConfigTable =3D NULL; >=20 > - >=20 > - RootBridgeNode =3D AllocateZeroPool (sizeof (BRIDGE_DEVICE_NODE)); >=20 > - if (RootBridgeNode =3D=3D NULL) { >=20 > - return EFI_OUT_OF_RESOURCES; >=20 > - } >=20 > - RootBridgeNode->Signature =3D PCI_ROOT_BRIDGE_DEVI= CE_SIGNATURE; >=20 > - RootBridgeNode->RootBridgeDevicePath =3D BridgePort->DevicePa= th; >=20 > - PciConfigTable =3D AllocateZeroPool ( >=20 > - sizeof (PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE) >=20 > - ); >=20 > - if (PciConfigTable) { >=20 > - PciConfigTable->ID =3D PortNumber; >=20 > - // >=20 > - // start by assuming 4096B as the default value for the Max. Payload= Size >=20 > - // >=20 > - PciConfigTable->Max_Payload_Size =3D PCIE_MAX_PAYLOAD_SIZ= E_4096B; >=20 > - // >=20 > - // start by assuming 4096B as the default value for the Max. Read Re= quest Size >=20 > - // >=20 > - PciConfigTable->Max_Read_Request_Size =3D PCIE_MAX_READ_REQ_SI= ZE_4096B; >=20 > - // >=20 > - // start by assuming the Max. Read Request Size need not be common f= or all >=20 > - // the devices in the PCI tree >=20 > - // >=20 > - PciConfigTable->Lock_Max_Read_Request_Size =3D FALSE; >=20 > - // >=20 > - // start by assuming the LTR mechanism is supported in a PCI tree >=20 > - // >=20 > - PciConfigTable->LtrSupported =3D TRUE; >=20 > - // >=20 > - // the default LTR mechanism is disabled as per the PCI Base specifi= cation >=20 > - // >=20 > - PciConfigTable->LtrEnable =3D FALSE; >=20 > - // >=20 > - // start by assuming the AtomicOp Routing capability is supported in= the PCI >=20 > - // tree >=20 > - // >=20 > - PciConfigTable->AtomicOpRoutingSupported =3D TRUE; >=20 > - // >=20 > - // start by assuming the Extended Tag is 10b Requester capable >=20 > - // >=20 > - PciConfigTable->ExtendedTag =3D EFI_PCI_EXPRESS_EXTE= NDED_TAG_10BIT; >=20 > - // >=20 > - // initial state set to ASPM L0s and L1 both >=20 > - // >=20 > - PciConfigTable->AspmSupport =3D EFI_PCI_EXPRESS_ASPM= _L0S_L1_SUPPORT; >=20 > - // >=20 > - // start by assuming less than 64ns of L0s Exit Latency >=20 > - // >=20 > - PciConfigTable->L0sExitLatency =3D PCIE_LINK_CAPABILITY= _L0S_EXIT_LATENCY_64NS; >=20 > - // >=20 > - // start by assuming less than 1us of L1 Exit Latency >=20 > - // >=20 > - PciConfigTable->L1ExitLatency =3D PCIE_LINK_CAPABILITY= _L1_EXIT_LATENCY_1US; >=20 > - // >=20 > - // default link retrain is not required >=20 > - // >=20 > - PciConfigTable->LinkReTrain =3D FALSE; >=20 > - // >=20 > - // start by assuming no common clock configuration mode for the devi= ce's link >=20 > - // >=20 > - PciConfigTable->CommonClockConfiguration =3D FALSE; >=20 > - } >=20 > - >=20 > - RootBridgeNode->PciExFeaturesConfigurationTable =3D PciConfigTable; >=20 > - >=20 > - InsertTailList (&mRootBridgeDeviceList, &RootBridgeNode->NextRootBridg= eDevice); >=20 > - >=20 > - if (PciConfigTable =3D=3D NULL) { >=20 > - return EFI_OUT_OF_RESOURCES; >=20 > - } >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Scan all the nodes of the RootBridge to identify and create a separate= list >=20 > - of all primary physical PCI root ports and link each with its own inst= ance of >=20 > - the PCI Feature Configuration Table. >=20 > - >=20 > - @param RootBridge A pointer to the PCI_IO_DEVICE of the PCI Root B= ridge >=20 > - >=20 > - @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to store PCI f= eature >=20 > - configuration table for all the physical= PCI root >=20 > - ports given >=20 > - EFI_NOT_FOUND No PCI Bridge device found >=20 > - EFI_SUCCESS PCI Feature COnfiguration table created = for all >=20 > - the PCI Rooot ports found >=20 > - EFI_INVALID_PARAMETER invalid parameter passed to the routine = which >=20 > - creates the PCI controller node for the = primary >=20 > - Root post list >=20 > -**/ >=20 > -EFI_STATUS >=20 > -CreatePciRootBridgeDeviceList ( >=20 > - IN PCI_IO_DEVICE *RootBridge >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status =3D EFI_NOT_FOUND; >=20 > - LIST_ENTRY *Link; >=20 > - PCI_IO_DEVICE *Device; >=20 > - UINTN BridgeDeviceCount; >=20 > - >=20 > - BridgeDeviceCount =3D 0; >=20 > - for ( Link =3D RootBridge->ChildList.ForwardLink >=20 > - ; Link !=3D &RootBridge->ChildList >=20 > - ; Link =3D Link->ForwardLink >=20 > - ) { >=20 > - Device =3D PCI_IO_DEVICE_FROM_LINK (Link); >=20 > - if (!DeviceExist (Device)) { >=20 > - continue; >=20 > - } >=20 > - if (IS_PCI_BRIDGE (&Device->Pci)) { >=20 > - BridgeDeviceCount++; >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "#%d ::Bridge [%02x|%02x|%02x]", >=20 > - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, Devi= ce->FunctionNumber >=20 > - )); >=20 > - // >=20 > - // create a list of bridge devices if that is connected to any oth= er device >=20 > - // >=20 > - if (!IsListEmpty (&Device->ChildList)) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "- has downstream device!\n" >=20 > - )); >=20 > - Status =3D CreatePciRootBridgeDeviceNode (Device, BridgeDeviceCo= unt); >=20 > - if (EFI_ERROR (Status)) { >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "PCI configuration table allocation failure for #%d ::Bridge= [%02x|%02x|%02x]\n", >=20 > - BridgeDeviceCount, Device->BusNumber, Device->DeviceNumber, = Device->FunctionNumber >=20 > - )); >=20 > - } >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "- no downstream device!\n" >=20 > - )); >=20 > - } >=20 > - } >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Initialize the device's PCI Express features, in a staged manner >=20 > - @param PciDevice A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS initializing all the nodes of the root b= ridge >=20 > - instances were successfull. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -InitializeDevicePciExpressFeatures ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - >=20 > - switch (PciConfigPhase) { >=20 > - case PciExpressFeatureSetupPhase: >=20 > - case PciExpressFeatureEntendedSetupPhase: >=20 > - case PciExpressFeatureProgramPhase: >=20 > - Status =3D SetupDevicePciExpressFeatures (PciDevice, PciConfigPhas= e); >=20 > - break; >=20 > - case PciExpressFeatureEndPhase: >=20 > - Status =3D PciExpressPlatformNotifyDeviceState (PciDevice); >=20 > - break; >=20 > - } >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Traverse all the nodes from the root bridge or PCI-PCI bridge instance= , to >=20 > - configure the PCI Express features as per the PCI Express Base Secific= ation >=20 > - by considering its device-specific platform policy, and its device cap= ability, >=20 > - as applicable. >=20 > - >=20 > - @param RootBridge A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS Traversing all the nodes of the root bri= dge >=20 > - instances were successfull. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -InitializePciExpressFeatures ( >=20 > - IN PCI_IO_DEVICE *RootBridge, >=20 > - IN PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciConfigPhase >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - LIST_ENTRY *Link; >=20 > - PCI_IO_DEVICE *Device; >=20 > - >=20 > - for ( Link =3D RootBridge->ChildList.ForwardLink >=20 > - ; Link !=3D &RootBridge->ChildList >=20 > - ; Link =3D Link->ForwardLink >=20 > - ) { >=20 > - Device =3D PCI_IO_DEVICE_FROM_LINK (Link); >=20 > - if (!DeviceExist (Device)) { >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "::Device [%02x|%02x|%02x] - does not exist!!!\n", >=20 > - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber >=20 > - )); >=20 > - continue; >=20 > - } >=20 > - if (IS_PCI_BRIDGE (&Device->Pci)) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "::Bridge [%02x|%02x|%02x] -", >=20 > - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber >=20 > - )); >=20 > - if (Device->IsPciExp) { >=20 > - Status =3D InitializeDevicePciExpressFeatures ( >=20 > - Device, >=20 > - PciConfigPhase >=20 > - ); >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Not a PCIe capable device!\n" >=20 > - )); >=20 > - // >=20 > - // PCI Bridge which does not have PCI Express Capability structu= re >=20 > - // cannot process this kind of PCI Bridge device >=20 > - // >=20 > - } >=20 > - >=20 > - InitializePciExpressFeatures (Device, PciConfigPhase); >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "::Device [%02x|%02x|%02x] -", >=20 > - Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber >=20 > - )); >=20 > - if (Device->IsPciExp) { >=20 > - Status =3D InitializeDevicePciExpressFeatures ( >=20 > - Device, >=20 > - PciConfigPhase >=20 > - ); >=20 > - } else { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Not a PCIe capable device!\n" >=20 > - )); >=20 > - // >=20 > - // PCI Device which does not have PCI Express Capability structu= re >=20 > - // cannot process this kind of PCI device >=20 > - // >=20 > - } >=20 > - } >=20 > - } >=20 > - >=20 > - return EFI_SUCCESS; >=20 > -} >=20 > - >=20 > -/** >=20 > - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge= , to >=20 > - configure the other PCI features. >=20 > - >=20 > - @param RootBridge A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS The other PCI features configuration dur= ing enumeration >=20 > - of all the nodes of the PCI root bridge = instance were >=20 > - programmed in PCI-compliance pattern alo= ng with the >=20 > - device-specific policy, as applicable. >=20 > - @retval EFI_UNSUPPORTED One of the override operation maong the = nodes of >=20 > - the PCI hierarchy resulted in a incompat= ible address >=20 > - range. >=20 > - @retval EFI_INVALID_PARAMETER The override operation is performed with= invalid input >=20 > - parameters. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -EnumeratePciExpressFeatures ( >=20 > - IN EFI_HANDLE Controller, >=20 > - IN PCI_IO_DEVICE *RootBridge >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - UINTN PciExpressFeatureConfigPhase; >=20 > - >=20 > - if (!IsPciExpressFeatureConfigurationRequired ()) { >=20 > - // >=20 > - // exit as agreement is not reached with platform to configure the P= CI >=20 > - // Express features >=20 > - // >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - mRootBridgeHandle =3D Controller; >=20 > - >=20 > - DEBUG_CODE ( >=20 > - CHAR16 *Str; >=20 > - Str =3D ConvertDevicePathToText ( >=20 > - DevicePathFromHandle (RootBridge->Handle), >=20 > - FALSE, >=20 > - FALSE >=20 > - ); >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "Enumerating PCI features for Root Bridge %s\n", >=20 > - Str !=3D NULL ? Str : L"" >=20 > - )); >=20 > - >=20 > - if (Str !=3D NULL) { >=20 > - FreePool (Str); >=20 > - } >=20 > - ); >=20 > - >=20 > - for ( PciExpressFeatureConfigPhase =3D PciExpressFeaturePreProcessPhas= e >=20 > - ; PciExpressFeatureConfigPhase <=3D PciExpressFeatureEndPhase >=20 > - ; PciExpressFeatureConfigPhase++ >=20 > - ) { >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "<<********** Phase [%d]**********>>\n", >=20 > - PciExpressFeatureConfigPhase >=20 > - )); >=20 > - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeaturePreProcessP= hase) { >=20 > - // >=20 > - // create a list of root bridge devices (root ports) of the root c= omplex >=20 > - // if extra setup phase required >=20 > - // >=20 > - if (IsPciExpressFeatureExtendedSetupRequired ()) { >=20 > - CreatePciRootBridgeDeviceList (RootBridge); >=20 > - } >=20 > - continue; >=20 > - } >=20 > - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeatureEntendedSet= upPhase) { >=20 > - if (!IsPciExpressFeatureExtendedSetupRequired ()) { >=20 > - // >=20 > - // since the PCI Express features require no extra initializatio= n steps >=20 > - // skip this phase >=20 > - // >=20 > - continue; >=20 > - } >=20 > - } >=20 > - // >=20 > - // setup the PCI Express features >=20 > - // >=20 > - Status =3D InitializePciExpressFeatures (RootBridge, PciExpressFeatu= reConfigPhase); >=20 > - >=20 > - if (PciExpressFeatureConfigPhase =3D=3D PciExpressFeatureEndPhase) { >=20 > - // >=20 > - // clean up the temporary resource nodes created for this root bri= dge >=20 > - // >=20 > - if (IsPciExpressFeatureExtendedSetupRequired ()) { >=20 > - DestroyRootBridgeDeviceNodes (); >=20 > - } >=20 > - } >=20 > - } >=20 > - >=20 > - return Status; >=20 > -} >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > deleted file mode 100644 > index 481bd90..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h > +++ /dev/null > @@ -1,304 +0,0 @@ > -/** @file >=20 > - PCI standard feature support functions implementation for PCI Bus modu= le.. >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > -#ifndef _EFI_PCI_FEATURES_SUPPORT_H_ >=20 > -#define _EFI_PCI_FEATURES_SUPPORT_H_ >=20 > - >=20 > -extern EFI_HANDLE mRootBridgeHandle; >=20 > -extern EFI_PCI_EXPRESS_PLATFORM_POLICY mPciExpressPlatformP= olicy; >=20 > -// >=20 > -// defines the data structure to hold the details of the PCI Root port d= evices >=20 > -// >=20 > -typedef struct _BRIDGE_DEVICE_NODE BRIDGE_DEVICE_NODE; >=20 > - >=20 > -// >=20 > -// defines the data structure to hold the configuration data for the oth= er PCI >=20 > -// features >=20 > -// >=20 > -typedef struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE PCI_EXPRESS_FE= ATURES_CONFIGURATION_TABLE; >=20 > - >=20 > -// >=20 > -// define the data type for the PCI feature policy support >=20 > -// >=20 > -typedef struct _PCI_FEATURE_POLICY PCI_FEATURE_POLICY; >=20 > - >=20 > -// >=20 > -// Signature value for the PCI Root Port node >=20 > -// >=20 > -#define PCI_ROOT_BRIDGE_DEVICE_SIGNATURE SIGNATURE_32 ('p'= , 'c', 'i', 'p') >=20 > - >=20 > -// >=20 > -// Definitions of the PCI Root Port data structure members >=20 > -// >=20 > -struct _BRIDGE_DEVICE_NODE { >=20 > - // >=20 > - // Signature header >=20 > - // >=20 > - UINT32 Signature; >=20 > - // >=20 > - // linked list pointers to next node >=20 > - // >=20 > - LIST_ENTRY NextRootBridgeDevice; >=20 > - // >=20 > - // pointer to PCI_IO_DEVICE of the primary PCI Controller device >=20 > - // >=20 > - EFI_DEVICE_PATH_PROTOCOL *RootBridgeDevicePath; >=20 > - // >=20 > - // pointer to the corresponding PCI Express feature configuration Tabl= e node >=20 > - // all the child PCI devices of the controller are aligned based on th= is table >=20 > - // >=20 > - PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE *PciExFeaturesConfigurationT= able; >=20 > -}; >=20 > - >=20 > -#define ROOT_BRIDGE_DEVICE_NODE_FROM_LINK(a) \ >=20 > - CR (a, BRIDGE_DEVICE_NODE, NextRootBridgeDevice, PCI_ROOT_BRIDGE_DEVIC= E_SIGNATURE) >=20 > - >=20 > -// >=20 > -// Definition of the PCI Feature configuration Table members >=20 > -// >=20 > -struct _PCI_EXPRESS_FEATURES_CONFIGURATION_TABLE { >=20 > - // >=20 > - // Configuration Table ID >=20 > - // >=20 > - UINTN ID; >=20 > - // >=20 > - // to configure the PCI feature Maximum payload size to maintain the d= ata packet >=20 > - // size among all the PCI devices in the PCI hierarchy >=20 > - // >=20 > - UINT8 Max_Payload_Size; >=20 > - // >=20 > - // to configure the PCI feature maximum read request size to maintain = the memory >=20 > - // requester size among all the PCI devices in the PCI hierarchy >=20 > - // >=20 > - UINT8 Max_Read_Request_Size; >=20 > - // >=20 > - // lock the Max_Read_Request_Size for the entire PCI tree of a root po= rt >=20 > - // >=20 > - BOOLEAN Lock_Max_Read_Request_Size; >=20 > - // >=20 > - // to record the adversity in LTR mechanism support capability among t= he PCI >=20 > - // device of an heirarchy >=20 > - // >=20 > - BOOLEAN LtrSupported; >=20 > - // >=20 > - // to enable the LTR mechansim for the entire PCI tree from a root por= t >=20 > - // >=20 > - BOOLEAN LtrEnable; >=20 > - // >=20 > - // to record the AtomicOp Routing capability of the PCI Heirarchy to e= nable >=20 > - // the AtomicOp of the EP device >=20 > - // >=20 > - BOOLEAN AtomicOpRoutingSupported; >=20 > - // >=20 > - // to configure a common extended tag size for all the childs of a roo= t port >=20 > - // >=20 > - UINT8 ExtendedTag; >=20 > - // >=20 > - // to configure common ASPM state for all the devices link >=20 > - // >=20 > - UINT8 AspmSupport; >=20 > - // >=20 > - // to record maximum L0s Exit Latency among all the devices starting f= rom root >=20 > - // bridge device to its downstream bridge and its endpoint device >=20 > - // >=20 > - UINT8 L0sExitLatency; >=20 > - // >=20 > - // to record maximum L1 Exit Latency among all the devices starting fr= om root >=20 > - // bridge device to its downstream bridge and its endpoint device >=20 > - // >=20 > - UINT8 L1ExitLatency; >=20 > - // >=20 > - // flag to indicate the link training is required in the devices of do= wnstream >=20 > - // ports >=20 > - // >=20 > - BOOLEAN LinkReTrain; >=20 > - // >=20 > - // link status slot clock configuration >=20 > - // >=20 > - BOOLEAN CommonClockConfiguration; >=20 > -}; >=20 > - >=20 > -// >=20 > -// Declaration of the internal sub-phases during enumeration to configur= e the PCI >=20 > -// Express features >=20 > -// >=20 > -typedef enum { >=20 > - // >=20 > - // preprocessing applicable only to few PCI Express features to bind a= ll devices >=20 > - // under the common root bridge device (root port), that would be usef= ul to align >=20 > - // all devices with a common value. This would be optional phase based= on the >=20 > - // type of the PCI Express feature to be programmed based on platform = policy >=20 > - // >=20 > - PciExpressFeaturePreProcessPhase, >=20 > - >=20 > - // >=20 > - // mandatory phase to setup the PCI Express feature to its applicable = attribute, >=20 > - // based on its device-specific platform policies, matching with its d= evice capabilities >=20 > - // >=20 > - PciExpressFeatureSetupPhase, >=20 > - >=20 > - // >=20 > - // optional phase primarily to align all devices, specially required w= hen PCI >=20 > - // switch is present in the hierarchy, applicable to certain few PCI E= xpress >=20 > - // features only >=20 > - // >=20 > - PciExpressFeatureEntendedSetupPhase, >=20 > - >=20 > - // >=20 > - // mandatory programming phase to complete the configuration of the PC= I Express >=20 > - // features >=20 > - // >=20 > - PciExpressFeatureProgramPhase, >=20 > - >=20 > - // >=20 > - // optional phase to clean up temporary buffers, like those that were = prepared >=20 > - // during the preprocessing phase above >=20 > - // >=20 > - PciExpressFeatureEndPhase >=20 > - >=20 > -}PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE; >=20 > - >=20 > -// >=20 > -// declaration for the data type to harbor the PCI feature policies >=20 > -// >=20 > -struct _PCI_FEATURE_POLICY { >=20 > - // >=20 > - // if set, it indicates the feature should be enabled >=20 > - // if clear, it indicates the feature should be disabled >=20 > - // >=20 > - UINT8 Act : 1; >=20 > - // >=20 > - // this field will be specific to feature, it can be implementation sp= ecific >=20 > - // or it can be reserved and remain unused >=20 > - // >=20 > - UINT8 Support : 6; >=20 > - // >=20 > - // if set indicates override the feature policy defined by the members= above >=20 > - // if clear it indicates that this feature policy should be ignored co= mpletely >=20 > - // this means the above two members should not be used >=20 > - // >=20 > - UINT8 Override : 1; >=20 > -}; >=20 > - >=20 > -// >=20 > -// Declaration of the PCI Express features unique Id >=20 > -// >=20 > -typedef enum { >=20 > - // >=20 > - // support for PCI Express feature - Max. Payload Size >=20 > - // >=20 > - PciExpressMps, >=20 > - // >=20 > - // support for PCI Express feature - Max. Read Request Size >=20 > - // >=20 > - PciExpressMrrs, >=20 > - // >=20 > - // support for PCI Express feature - Extended Tag >=20 > - // >=20 > - PciExpressExtTag, >=20 > - // >=20 > - // support for PCI Express feature - Relax Order >=20 > - // >=20 > - PciExpressRelaxOrder, >=20 > - // >=20 > - // support for PCI Express feature - No-Snoop >=20 > - // >=20 > - PciExpressNoSnoop, >=20 > - // >=20 > - // support for PCI Express feature - ASPM state >=20 > - // >=20 > - PciExpressAspm, >=20 > - // >=20 > - // support for PCI Express feature - Common Clock Configuration >=20 > - // >=20 > - PciExpressCcc, >=20 > - // >=20 > - // support for PCI Express feature - Extended Sync >=20 > - // >=20 > - PciExpressExtSync, >=20 > - // >=20 > - // support for PCI Express feature - Atomic Op >=20 > - // >=20 > - PciExpressAtomicOp, >=20 > - // >=20 > - // support for PCI Express feature - LTR >=20 > - // >=20 > - PciExpressLtr, >=20 > - // >=20 > - // support for PCI Express feature - PTM >=20 > - // >=20 > - PciExpressPtm, >=20 > - // >=20 > - // support for PCI Express feature - Completion Timeout >=20 > - // >=20 > - PciExpressCto, >=20 > - // >=20 > - // support for PCI Express feature - Clock Power Management >=20 > - // >=20 > - PciExpressCpm, >=20 > - // >=20 > - // support for PCI Express feature - L1 PM Substates >=20 > - // >=20 > - PciExpressL1PmSubstates >=20 > - >=20 > -} PCI_EXPRESS_FEATURE_ID; >=20 > - >=20 > -// >=20 > -// PCI Express feature configuration routine during initialization phase= s >=20 > -// >=20 > -typedef >=20 > -EFI_STATUS >=20 > -(*PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE) ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN VOID *PciExpressFeatureConfigur= ation >=20 > - ); >=20 > - >=20 > -// >=20 > -// data type for the PCI Express feature initialization phases >=20 > -// >=20 > -typedef struct { >=20 > - // >=20 > - // Pci Express feature configuration phase >=20 > - // >=20 > - PCI_EXPRESS_FEATURE_CONFIGURATION_PHASE PciExpressFeatureConfigurati= onPhase; >=20 > - // >=20 > - // PCI Express feature Id >=20 > - // >=20 > - PCI_EXPRESS_FEATURE_ID PciExpressFeatureId; >=20 > - // >=20 > - // PCI Express feature configuration routine >=20 > - // >=20 > - PCI_EXPRESS_FEATURE_CONFIGURATION_ROUTINE PciExpressFeatureConfigurati= onRoutine; >=20 > - >=20 > -}PCI_EXPRESS_FEATURE_INITIALIZATION_POINT; >=20 > - >=20 > - >=20 > - >=20 > -/** >=20 > - Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge= , to >=20 > - configure the other PCI features. >=20 > - >=20 > - @param RootBridge A pointer to the PCI_IO_DEVICE. >=20 > - >=20 > - @retval EFI_SUCCESS The other PCI features configuration dur= ing enumeration >=20 > - of all the nodes of the PCI root bridge = instance were >=20 > - programmed in PCI-compliance pattern alo= ng with the >=20 > - device-specific policy, as applicable. >=20 > - @retval EFI_UNSUPPORTED One of the override operation maong the = nodes of >=20 > - the PCI hierarchy resulted in a incompat= ible address >=20 > - range. >=20 > - @retval EFI_INVALID_PARAMETER The override operation is performed with= invalid input >=20 > - parameters. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -EnumeratePciExpressFeatures ( >=20 > - IN EFI_HANDLE Controller, >=20 > - IN PCI_IO_DEVICE *RootBridge >=20 > - ); >=20 > - >=20 > -#endif >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > deleted file mode 100644 > index bf380ab..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c > +++ /dev/null > @@ -1,902 +0,0 @@ > -/** @file >=20 > - This file encapsulate the usage of PCI Platform Protocol >=20 > - >=20 > - This file define the necessary hooks used to obtain the platform >=20 > - level data and policies which could be used in the PCI Enumeration pha= ses >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > -#include "PciBus.h" >=20 > - >=20 > - >=20 > -EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *mPciExPlatformProtocol; >=20 > -EFI_PCI_EXPRESS_OVERRIDE_PROTOCOL *mPciExOverrideProtocol; >=20 > - >=20 > - >=20 > -/** >=20 > - This function retrieves the PCI Express Platform Protocols published b= y platform >=20 > - @retval EFI_STATUS direct return status from the LocateProtoc= ol () >=20 > - boot service for the PCI Express Override = Protocol >=20 > - EFI_SUCCESS The PCI Express Platform Protocol is found >=20 > -**/ >=20 > -EFI_STATUS >=20 > -GetPciExpressProtocol ( >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - >=20 > - if (mPciExPlatformProtocol) { >=20 > - // >=20 > - // the PCI Express Platform Protocol is already initialized >=20 > - // >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - if (mPciExOverrideProtocol) { >=20 > - // >=20 > - // the PCI Express Override Protocol is already initialized >=20 > - // >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - // >=20 > - // locate the PCI Express Platform Protocol >=20 > - // >=20 > - Status =3D gBS->LocateProtocol ( >=20 > - &gEfiPciExpressPlatformProtocolGuid, >=20 > - NULL, >=20 > - (VOID **) &mPciExPlatformProtocol >=20 > - ); >=20 > - if (!EFI_ERROR (Status)) { >=20 > - return Status; >=20 > - } >=20 > - // >=20 > - // If PCI Express Platform protocol doesn't exist, try to get the Pci = Express >=20 > - // Override Protocol. >=20 > - // >=20 > - return gBS->LocateProtocol ( >=20 > - &gEfiPciExpressOverrideProtocolGuid, >=20 > - NULL, >=20 > - (VOID **) &mPciExOverrideProtocol >=20 > - ); >=20 > -} >=20 > - >=20 > -/** >=20 > - This function indicates that the platform has published the PCI Expres= s Platform >=20 > - Protocol (or PCI Express Override Protocol) to indicate that this driv= er can >=20 > - initialize the PCI Express features. >=20 > - @retval TRUE or FALSE >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsPciExpressProtocolPresent ( >=20 > - ) >=20 > -{ >=20 > - if ( >=20 > - mPciExPlatformProtocol =3D=3D NULL >=20 > - && mPciExOverrideProtocol =3D=3D NULL >=20 > - ) { >=20 > - return FALSE; >=20 > - } >=20 > - return TRUE; >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to translate the given device-specific platform policy from ty= pe >=20 > - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base= Specification >=20 > - Revision 4.0; for the PCI feature Max_Payload_Size. >=20 > - >=20 > - @param MPS Input device-specific policy should be in terms of typ= e >=20 > - EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE >=20 > - >=20 > - @retval Range values for the Max_Payload_Size as defined in th= e PCI >=20 > - Base Specification 4.0 >=20 > -**/ >=20 > -UINT8 >=20 > -SetDevicePolicyPciExpressMps ( >=20 > - IN UINT8 MPS >=20 > -) >=20 > -{ >=20 > - switch (MPS) { >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_128B; >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_256B; >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_512B; >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_1024B; >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_2048B; >=20 > - case EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_4096B; >=20 > - default: >=20 > - return PCIE_MAX_PAYLOAD_SIZE_128B; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to translate the given device-specific platform policy from ty= pe >=20 > - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Bas= e Specification >=20 > - Revision 4.0; for the PCI feature Max_Read_Req_Size. >=20 > - >=20 > - @param MRRS Input device-specific policy should be in terms of typ= e >=20 > - EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE >=20 > - >=20 > - @retval Range values for the Max_Read_Req_Size as defined in t= he PCI >=20 > - Base Specification 4.0 >=20 > -**/ >=20 > -UINT8 >=20 > -SetDevicePolicyPciExpressMrrs ( >=20 > - IN UINT8 MRRS >=20 > -) >=20 > -{ >=20 > - switch (MRRS) { >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_128B; >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_256B; >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_512B; >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_1024B; >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_2048B; >=20 > - case EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B: >=20 > - return PCIE_MAX_READ_REQ_SIZE_4096B; >=20 > - default: >=20 > - return PCIE_MAX_READ_REQ_SIZE_128B; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to set the device-specific policy for the PCI feature Relax Or= dering >=20 > - >=20 > - @param RelaxOrder value corresponding to data type EFI_PCI_EXPRESS= _RELAX_ORDER >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > -**/ >=20 > -VOID >=20 > -SetDevicePolicyPciExpressRo ( >=20 > - IN EFI_PCI_EXPRESS_RELAX_ORDER RelaxOrder, >=20 > - OUT PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // implementation specific rules for the usage of PCI_FEATURE_POLICY m= embers >=20 > - // exclusively for the PCI Feature Relax Ordering (RO) >=20 > - // >=20 > - // .Override =3D 0 to skip this PCI feature RO for the PCI device >=20 > - // .Override =3D 1 to program this RO PCI feature >=20 > - // .Act =3D 1 to enable the RO in the PCI device >=20 > - // .Act =3D 0 to disable the RO in the PCI device >=20 > - // >=20 > - switch (RelaxOrder) { >=20 > - case EFI_PCI_EXPRESS_RO_AUTO: >=20 > - PciDevice->SetupRO.Override =3D 0; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_RO_DISABLE: >=20 > - PciDevice->SetupRO.Override =3D 1; >=20 > - PciDevice->SetupRO.Act =3D 0; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_RO_ENABLE: >=20 > - PciDevice->SetupRO.Override =3D 1; >=20 > - PciDevice->SetupRO.Act =3D 1; >=20 > - break; >=20 > - default: >=20 > - PciDevice->SetupRO.Override =3D 0; >=20 > - break; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to set the device-specific policy for the PCI feature No-Snoop= enable >=20 > - or disable >=20 > - >=20 > - @param NoSnoop value corresponding to data type EFI_PCI_EXPRESS= _NO_SNOOP >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > -**/ >=20 > -VOID >=20 > -SetDevicePolicyPciExpressNs ( >=20 > - IN EFI_PCI_EXPRESS_NO_SNOOP NoSnoop, >=20 > - OUT PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - // >=20 > - // implementation specific rules for the usage of PCI_FEATURE_POLICY m= embers >=20 > - // exclusively for the PCI Feature No-Snoop >=20 > - // >=20 > - // .Override =3D 0 to skip this PCI feature No-Snoop for the PCI devic= e >=20 > - // .Override =3D 1 to program this No-Snoop PCI feature >=20 > - // .Act =3D 1 to enable the No-Snoop in the PCI device >=20 > - // .Act =3D 0 to disable the No-Snoop in the PCI device >=20 > - // >=20 > - switch (NoSnoop) { >=20 > - case EFI_PCI_EXPRESS_NS_AUTO: >=20 > - PciDevice->SetupNS.Override =3D 0; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_NS_DISABLE: >=20 > - PciDevice->SetupNS.Override =3D 1; >=20 > - PciDevice->SetupNS.Act =3D 0; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_NS_ENABLE: >=20 > - PciDevice->SetupNS.Override =3D 1; >=20 > - PciDevice->SetupNS.Act =3D 1; >=20 > - break; >=20 > - default: >=20 > - PciDevice->SetupNS.Override =3D 0; >=20 > - break; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to set the device-specific policy for the PCI feature CTO valu= e range >=20 > - or disable >=20 > - >=20 > - @param CtoSupport value corresponding to data type EFI_PCI_EXPRESS= _CTO_SUPPORT >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > -**/ >=20 > -VOID >=20 > -SetDevicePolicyPciExpressCto ( >=20 > - IN EFI_PCI_EXPRESS_CTO_SUPPORT CtoSupport, >=20 > - OUT PCI_IO_DEVICE *PciDevice >=20 > -) >=20 > -{ >=20 > - // >=20 > - // implementation specific rules for the usage of PCI_FEATURE_POLICY m= embers >=20 > - // exclusively for the PCI Feature CTO >=20 > - // >=20 > - // .Override =3D 0 to skip this PCI feature CTO for the PCI device >=20 > - // .Override =3D 1 to program this CTO PCI feature >=20 > - // .Act =3D 1 to program the CTO range as per given device policy= in .Support >=20 > - // .Act =3D 0 to disable the CTO mechanism in the PCI device, CTO= set to default range >=20 > - // >=20 > - switch (CtoSupport) { >=20 > - case EFI_PCI_EXPRESS_CTO_AUTO: >=20 > - PciDevice->SetupCTO.Override =3D 0; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_DEFAULT: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_A1: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_100US= ; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_A2: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1MS_10MS; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_B1: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_16MS_55MS; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_B2: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS= ; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_C1: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_260MS_900M= S; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_C2: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_D1: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_4S_13S; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_RANGE_D2: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 1; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_17S_64S; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_CTO_DET_DISABLE: >=20 > - PciDevice->SetupCTO.Override =3D 1; >=20 > - PciDevice->SetupCTO.Act =3D 0; >=20 > - PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; >=20 > - break; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Routine to set the device-specific policy for the PCI feature LTR enab= le/disable >=20 > - >=20 > - @param AtomicOp value corresponding to data type EFI_PCI_EXPRESS= _ATOMIC_OP >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - >=20 > -**/ >=20 > -VOID >=20 > -SetDevicePolicyPciExpressLtr ( >=20 > - IN EFI_PCI_EXPRESS_LTR Ltr, >=20 > - OUT PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - switch (Ltr){ >=20 > - case EFI_PCI_EXPRESS_LTR_AUTO: >=20 > - case EFI_PCI_EXPRESS_LTR_DISABLE: >=20 > - // >=20 > - // leave the LTR mechanism disable or restore to its default state >=20 > - // >=20 > - PciDevice->SetupLtr =3D FALSE; >=20 > - break; >=20 > - case EFI_PCI_EXPRESS_LTR_ENABLE: >=20 > - // >=20 > - // LTR mechanism enable >=20 > - // >=20 > - PciDevice->SetupLtr =3D TRUE; >=20 > - break; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Generic routine to setup the PCI features as per its predetermined def= aults. >=20 > -**/ >=20 > -VOID >=20 > -SetupDefaultPciExpressDevicePolicy ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - >=20 > - if (mPciExpressPlatformPolicy.Mps) { >=20 > - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_AUTO; >=20 > - } else { >=20 > - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - if (mPciExpressPlatformPolicy.Mrrs) { >=20 > - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_AUTO; >=20 > - } else { >=20 > - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - PciDevice->SetupRO.Override =3D 0; >=20 > - >=20 > - PciDevice->SetupNS.Override =3D 0; >=20 > - >=20 > - PciDevice->SetupCTO.Override =3D 0; >=20 > - >=20 > - PciDevice->SetupAtomicOp.Override =3D 0; >=20 > - >=20 > - PciDevice->SetupLtr =3D FALSE; >=20 > - >=20 > - if (mPciExpressPlatformPolicy.ExtTag) { >=20 > - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_EXTENDED_TAG_AUTO; >=20 > - } else { >=20 > - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // default device policy for device's link ASPM >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Aspm) { >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_ASPM_AUTO; >=20 > - } else { >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // default device policy for the device's link clock configuration >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Ccc) { >=20 > - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_CLK_CFG_AUTO; >=20 > - } else { >=20 > - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > -} >=20 > - >=20 > -/** >=20 > - initialize the device policy data members >=20 > -**/ >=20 > -VOID >=20 > -InitializeDevicePolicyData ( >=20 > - IN EFI_PCI_EXPRESS_DEVICE_POLICY *PciExpressDevicePolicy >=20 > - ) >=20 > -{ >=20 > - UINTN length; >=20 > - UINT8 *PciExpressPolicy; >=20 > - UINT8 *PciExDevicePolicy; >=20 > - >=20 > - >=20 > - ZeroMem (PciExpressDevicePolicy, sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY= )); >=20 > - >=20 > - for ( >=20 > - length =3D 0 >=20 > - , PciExpressPolicy =3D (UINT8*)&mPciExpressPlatformPolicy >=20 > - , PciExDevicePolicy =3D (UINT8*)PciExpressDevicePolicy >=20 > - ; length < sizeof (EFI_PCI_EXPRESS_PLATFORM_POLICY) >=20 > - ; length++ >=20 > - ) { >=20 > - if (!PciExpressPolicy[length]) { >=20 > - PciExDevicePolicy[length] =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - Intermediate routine to either get the PCI device specific platform po= licies >=20 > - through the PCI Platform Protocol, or its alias the PCI Override Proto= col. >=20 > - >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - @param PciPlatformProtocol A pointer to EFI_PCI_EXPRESS_PLATFORM_PROT= OCOL >=20 > - >=20 > - @retval EFI_STATUS The direct status from the PCI Platform Pr= otocol >=20 > - @retval EFI_SUCCESS if on returning predetermined PCI features= defaults, >=20 > - for the case when protocol returns as EFI_= UNSUPPORTED >=20 > - to indicate PCI device exist and it has no= platform >=20 > - policy defined. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -GetPciExpressDevicePolicy ( >=20 > - IN PCI_IO_DEVICE *PciDevice, >=20 > - IN EFI_PCI_EXPRESS_PLATFORM_PROTOCOL *PciPlatformProtocol >=20 > - ) >=20 > -{ >=20 > - EFI_PCI_EXPRESS_DEVICE_POLICY PciExpressDevicePolicy; >=20 > - EFI_STATUS Status; >=20 > - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress; >=20 > - >=20 > - PciAddress.Bus =3D PciDevice->BusNumber; >=20 > - PciAddress.Device =3D PciDevice->DeviceNumber; >=20 > - PciAddress.Function =3D PciDevice->FunctionNumber; >=20 > - PciAddress.Register =3D 0; >=20 > - PciAddress.ExtendedRegister =3D 0; >=20 > - >=20 > - InitializeDevicePolicyData (&PciExpressDevicePolicy); >=20 > - Status =3D PciPlatformProtocol->GetDevicePolicy ( >=20 > - PciPlatformProtocol, >=20 > - mRootBridgeHandle, >=20 > - PciAddress, >=20 > - sizeof (EFI_PCI_EXPRESS_DEVICE_POLICY)= , >=20 > - &PciExpressDevicePolicy >=20 > - ); >=20 > - if (!EFI_ERROR(Status)) { >=20 > - // >=20 > - // platform chipset policies are returned for this PCI device >=20 > - // >=20 > - >=20 > - // >=20 > - // set device specific policy for the Max_Payload_Size >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Mps) { >=20 > - PciDevice->SetupMPS =3D PciExpressDevicePolicy.DeviceCtlMPS; >=20 > - } else { >=20 > - PciDevice->SetupMPS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // set device specific policy for Max_Read_Req_Size >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Mrrs) { >=20 > - PciDevice->SetupMRRS =3D PciExpressDevicePolicy.DeviceCtlMRRS; >=20 > - } else { >=20 > - PciDevice->SetupMRRS =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - // >=20 > - // set device specific policy for Relax Ordering >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.RelaxOrder) { >=20 > - SetDevicePolicyPciExpressRo (PciExpressDevicePolicy.DeviceCtlRelax= Order, PciDevice); >=20 > - } else { >=20 > - PciDevice->SetupRO.Override =3D 0; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device specific policy for No-Snoop >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.NoSnoop) { >=20 > - SetDevicePolicyPciExpressNs (PciExpressDevicePolicy.DeviceCtlNoSno= op, PciDevice); >=20 > - } else { >=20 > - PciDevice->SetupNS.Override =3D 0; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device specific policy for Completion Timeout (CTO) >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Cto) { >=20 > - SetDevicePolicyPciExpressCto (PciExpressDevicePolicy.CTOsupport, P= ciDevice); >=20 > - } else { >=20 > - PciDevice->SetupCTO.Override =3D 0; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device-specific policy for AtomicOp >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.AtomicOp) { >=20 > - PciDevice->SetupAtomicOp =3D PciExpressDevicePolicy.DeviceCtl2Atom= icOp; >=20 > - } else { >=20 > - PciDevice->SetupAtomicOp.Override =3D 0; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device-specific policy for LTR mechanism in the function >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Ltr) { >=20 > - SetDevicePolicyPciExpressLtr (PciExpressDevicePolicy.DeviceCtl2LTR= , PciDevice); >=20 > - } else { >=20 > - PciDevice->SetupLtr =3D FALSE; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device-specifci policy for the PCI Express feature Extend= ed Tag >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.ExtTag) { >=20 > - PciDevice->SetupExtTag =3D PciExpressDevicePolicy.DeviceCtlExtTag; >=20 > - } else { >=20 > - PciDevice->SetupExtTag =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device-specific policy for the PCI Express feature ASPM >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Aspm) { >=20 > - PciDevice->SetupAspm =3D PciExpressDevicePolicy.LinkCtlASPMState; >=20 > - } else { >=20 > - PciDevice->SetupAspm =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // set the device policy for the PCI Express feature Common Clock Co= nfiguration >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Ccc) { >=20 > - PciDevice->SetupCcc =3D PciExpressDevicePolicy.LinkCtlCommonClkCfg= ; >=20 > - } else { >=20 > - PciDevice->SetupCcc =3D EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > - } >=20 > - >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "[device policy: platform]" >=20 > - )); >=20 > - return Status; >=20 > - } else if (Status =3D=3D EFI_UNSUPPORTED) { >=20 > - // >=20 > - // platform chipset policies are not provided for this PCI device >=20 > - // let the enumeration happen as per the PCI standard way >=20 > - // >=20 > - SetupDefaultPciExpressDevicePolicy (PciDevice); >=20 > - DEBUG (( >=20 > - DEBUG_INFO, >=20 > - "[device policy: default]" >=20 > - )); >=20 > - return EFI_SUCCESS; >=20 > - } >=20 > - DEBUG (( >=20 > - DEBUG_ERROR, >=20 > - "[device policy: none (error)]" >=20 > - )); >=20 > - return Status; >=20 > -} >=20 > - >=20 > -/** >=20 > - Gets the PCI device-specific platform policy from the PCI Express Plat= form Protocol. >=20 > - If no PCI Platform protocol is published than setup the PCI feature to= predetermined >=20 > - defaults, in order to align all the PCI devices in the PCI hierarchy, = as applicable. >=20 > - >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - >=20 > - @retval EFI_STATUS The direct status from the PCI Platform Protocol >=20 > - @retval EFI_SUCCESS On return of predetermined PCI features defaults= , for >=20 > - the case when protocol returns as EFI_UNSUPPORTE= D to >=20 > - indicate PCI device exist and it has no platform= policy >=20 > - defined. Also, on returns when no PCI Platform P= rotocol >=20 > - exist. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformGetDevicePolicy ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - if (mPciExPlatformProtocol !=3D NULL) { >=20 > - return GetPciExpressDevicePolicy (PciDevice, mPciExPlatformProtocol)= ; >=20 > - } else if (mPciExOverrideProtocol !=3D NULL) { >=20 > - return GetPciExpressDevicePolicy (PciDevice, mPciExOverrideProtocol)= ; >=20 > - } else { >=20 > - // >=20 > - // no protocol found, platform does not require the PCI Express init= ialization >=20 > - // >=20 > - return EFI_UNSUPPORTED; >=20 > - } >=20 > -} >=20 > - >=20 > -/** >=20 > - This function gets the platform requirement to initialize the list of = PCI Express >=20 > - features from the protocol definition supported. >=20 > - This function should be called after the LocatePciPlatformProtocol. >=20 > - @retval EFI_SUCCESS return by platform to acknowledge the li= st of >=20 > - PCI Express feature to be configured >=20 > - (in mPciExpressPlatformPolicy) >=20 > - EFI_INVALID_PARAMETER platform does not support the protocol a= rguements >=20 > - passed >=20 > - EFI_UNSUPPORTED platform did not published the protocol >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformGetPolicy ( >=20 > - ) >=20 > -{ >=20 > - EFI_STATUS Status; >=20 > - >=20 > - if (mPciExPlatformProtocol) { >=20 > - Status =3D mPciExPlatformProtocol->GetPolicy ( >=20 > - mPciExPlatformProtocol, >=20 > - sizeof (EFI_PCI_EXPRESS_PLATFORM_P= OLICY), >=20 > - &mPciExpressPlatformPolicy >=20 > - ); >=20 > - } else if (mPciExOverrideProtocol) { >=20 > - Status =3D mPciExOverrideProtocol->GetPolicy ( >=20 > - mPciExOverrideProtocol, >=20 > - sizeof (EFI_PCI_EXPRESS_PLATFORM_P= OLICY), >=20 > - &mPciExpressPlatformPolicy >=20 > - ); >=20 > - } else { >=20 > - // >=20 > - // no protocol found, platform does not require the PCI Express init= ialization >=20 > - // >=20 > - return EFI_UNSUPPORTED; >=20 > - } >=20 > - return Status; >=20 > -} >=20 > - >=20 > -EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE >=20 > -GetPciExpressMps ( >=20 > - IN UINT8 Mps >=20 > - ) >=20 > -{ >=20 > - switch (Mps) { >=20 > - case PCIE_MAX_PAYLOAD_SIZE_128B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_128B; >=20 > - case PCIE_MAX_PAYLOAD_SIZE_256B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_256B; >=20 > - case PCIE_MAX_PAYLOAD_SIZE_512B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_512B; >=20 > - case PCIE_MAX_PAYLOAD_SIZE_1024B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_1024B; >=20 > - case PCIE_MAX_PAYLOAD_SIZE_2048B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_2048B; >=20 > - case PCIE_MAX_PAYLOAD_SIZE_4096B: >=20 > - return EFI_PCI_EXPRESS_MAX_PAYLOAD_SIZE_4096B; >=20 > - } >=20 > - return EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > -} >=20 > - >=20 > -EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE >=20 > -GetPciExpressMrrs ( >=20 > - IN UINT8 Mrrs >=20 > - ) >=20 > -{ >=20 > - switch (Mrrs) { >=20 > - case PCIE_MAX_READ_REQ_SIZE_128B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_128B; >=20 > - case PCIE_MAX_READ_REQ_SIZE_256B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_256B; >=20 > - case PCIE_MAX_READ_REQ_SIZE_512B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_512B; >=20 > - case PCIE_MAX_READ_REQ_SIZE_1024B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_1024B; >=20 > - case PCIE_MAX_READ_REQ_SIZE_2048B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_2048B; >=20 > - case PCIE_MAX_READ_REQ_SIZE_4096B: >=20 > - return EFI_PCI_EXPRESS_MAX_READ_REQ_SIZE_4096B; >=20 > - } >=20 > - return EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > -} >=20 > - >=20 > -EFI_PCI_EXPRESS_CTO_SUPPORT >=20 > -GetPciExpressCto ( >=20 > - IN UINT8 Cto >=20 > - ) >=20 > -{ >=20 > - switch (Cto) { >=20 > - case PCIE_COMPLETION_TIMEOUT_50US_50MS: >=20 > - return EFI_PCI_EXPRESS_CTO_DEFAULT; >=20 > - case PCIE_COMPLETION_TIMEOUT_50US_100US: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_A1; >=20 > - case PCIE_COMPLETION_TIMEOUT_1MS_10MS: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_A2; >=20 > - case PCIE_COMPLETION_TIMEOUT_16MS_55MS: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_B1; >=20 > - case PCIE_COMPLETION_TIMEOUT_65MS_210MS: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_B2; >=20 > - case PCIE_COMPLETION_TIMEOUT_260MS_900MS: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_C1; >=20 > - case PCIE_COMPLETION_TIMEOUT_1S_3_5S: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_C2; >=20 > - case PCIE_COMPLETION_TIMEOUT_4S_13S: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_D1; >=20 > - case PCIE_COMPLETION_TIMEOUT_17S_64S: >=20 > - return EFI_PCI_EXPRESS_CTO_RANGE_D2; >=20 > - } >=20 > - return EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > -} >=20 > - >=20 > -EFI_PCI_EXPRESS_EXTENDED_TAG >=20 > -GetPciExpressExtTag ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - if (PciDevice->PciExpressCapabilityStructure.DeviceControl2.Bits.TenBi= tTagRequesterEnable) { >=20 > - return EFI_PCI_EXPRESS_EXTENDED_TAG_10BIT; >=20 > - } else if (PciDevice->PciExpressCapabilityStructure.DeviceControl.Bits= .ExtendedTagField) { >=20 > - return EFI_PCI_EXPRESS_EXTENDED_TAG_8BIT; >=20 > - } else { >=20 > - return EFI_PCI_EXPRESS_EXTENDED_TAG_5BIT; >=20 > - } >=20 > -} >=20 > - >=20 > -EFI_PCI_EXPRESS_ASPM_SUPPORT >=20 > -GetPciExpressAspmState ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - switch (PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.Aspm= Control) { >=20 > - case 0: >=20 > - return EFI_PCI_EXPRESS_ASPM_DISABLE; >=20 > - case 1: >=20 > - return EFI_PCI_EXPRESS_ASPM_L0s_SUPPORT; >=20 > - case 2: >=20 > - return EFI_PCI_EXPRESS_ASPM_L1_SUPPORT; >=20 > - case 3: >=20 > - return EFI_PCI_EXPRESS_ASPM_L0S_L1_SUPPORT; >=20 > - } >=20 > - return EFI_PCI_EXPRESS_NOT_APPLICABLE; >=20 > -} >=20 > - >=20 > -/** >=20 > - Notifies the platform about the current PCI Express state of the devic= e. >=20 > - >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CO= NFIGURATION. >=20 > - Used to pass the current state of de= vice to >=20 > - platform. >=20 > - >=20 > - @retval EFI_STATUS The direct status from the PCI Express Platf= orm Protocol >=20 > - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protoc= ol or its >=20 > - alias PCI Express OVerride Protocol is not p= resent. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformNotifyDeviceState ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ) >=20 > -{ >=20 > - EFI_PCI_EXPRESS_DEVICE_CONFIGURATION PciExDeviceConfiguration; >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCIe Max_Payload_Size feature >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Mps) { >=20 > - PciExDeviceConfiguration.DeviceCtlMPS =3D GetPciExpressMps ( >=20 > - (UINT8)PciDevice->PciExpre= ssCapabilityStructure.DeviceControl.Bits.MaxPayloadSize >=20 > - ); >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtlMPS =3D EFI_PCI_EXPRESS_NOT_APPLIC= ABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCIe Max_Read_Req_Size featur= e >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Mrrs) { >=20 > - PciExDeviceConfiguration.DeviceCtlMRRS =3D GetPciExpressMrrs ( >=20 > - (UINT8)PciDevice->PciExpre= ssCapabilityStructure.DeviceControl.Bits.MaxReadRequestSize >=20 > - ); >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtlMRRS =3D EFI_PCI_EXPRESS_NOT_APPLI= CABLE; >=20 > - } >=20 > - // >=20 > - // get the device-specific state for the PCIe Relax Order feature >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.RelaxOrder) { >=20 > - PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D PciDevice- > >PciExpressCapabilityStructure.DeviceControl.Bits.RelaxedOrdering >=20 > - ? EFI_PCI_EXPRESS_= RO_ENABLE >=20 > - : EFI_PCI_EXPRESS_= RO_DISABLE; >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtlRelaxOrder =3D EFI_PCI_EXPRESS_NOT= _APPLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCIe NoSnoop feature >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.NoSnoop) { >=20 > - PciExDeviceConfiguration.DeviceCtlNoSnoop =3D PciDevice->PciExpressC= apabilityStructure.DeviceControl.Bits.NoSnoop >=20 > - ? EFI_PCI_EXPRESS_NS= _ENABLE >=20 > - : EFI_PCI_EXPRESS_NS= _DISABLE; >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtlNoSnoop =3D EFI_PCI_EXPRESS_NOT_AP= PLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCIe CTO feature >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Cto) { >=20 > - PciExDeviceConfiguration.CTOsupport =3D PciDevice- > >PciExpressCapabilityStructure.DeviceControl2.Bits.CompletionTimeoutDisab= le >=20 > - ? EFI_PCI_EXPRESS_CTO_DET_DISA= BLE >=20 > - : GetPciExpressCto ( >=20 > - (UINT8)PciDevice->PciExpre= ssCapabilityStructure.DeviceControl2.Bits.CompletionTimeoutValue >=20 > - ); >=20 > - } else { >=20 > - PciExDeviceConfiguration.CTOsupport =3D EFI_PCI_EXPRESS_NOT_APPLICAB= LE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCIe AtomicOp feature >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.AtomicOp) { >=20 > - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester >=20 > - =3D (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.B= its.AtomicOpRequester; >=20 > - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlo= cking >=20 > - =3D (UINT8)PciDevice->PciExpressCapabilityStructure.DeviceControl2.B= its.AtomicOpEgressBlocking; >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Override =3D 0; >=20 > - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpRequester= =3D 0; >=20 > - PciExDeviceConfiguration.DeviceCtl2AtomicOp.Enable_AtomicOpEgressBlo= cking =3D 0; >=20 > - } >=20 > - // >=20 > - // get the device-specific state for LTR mechanism in the function >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Ltr) { >=20 > - PciExDeviceConfiguration.DeviceCtl2LTR =3D PciDevice->PciExpressCapa= bilityStructure.DeviceControl2.Bits.LtrMechanism >=20 > - ? EFI_PCI_EXPRESS_LTR_EN= ABLE >=20 > - : EFI_PCI_EXPRESS_LTR_DI= SABLE; >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtl2LTR =3D EFI_PCI_EXPRESS_NOT_APPLI= CABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for the PCie Extended Tag in the func= tion >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.ExtTag) { >=20 > - PciExDeviceConfiguration.DeviceCtlExtTag =3D GetPciExpressExtTag (Pc= iDevice); >=20 > - } else { >=20 > - PciExDeviceConfiguration.DeviceCtlExtTag =3D EFI_PCI_EXPRESS_NOT_APP= LICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific state for PCIe ASPM state >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Aspm) { >=20 > - PciExDeviceConfiguration.LinkCtlASPMState =3D GetPciExpressAspmState= (PciDevice); >=20 > - } else { >=20 > - PciExDeviceConfiguration.LinkCtlASPMState =3D EFI_PCI_EXPRESS_NOT_AP= PLICABLE; >=20 > - } >=20 > - >=20 > - // >=20 > - // get the device-specific Common CLock Configuration value >=20 > - // >=20 > - if (mPciExpressPlatformPolicy.Ccc) { >=20 > - PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D >=20 > - PciDevice->PciExpressCapabilityStructure.LinkControl.Bits.Common= ClockConfiguration ? >=20 > - EFI_PCI_EXPRESS_CLK_CFG_COMMON : EFI_PCI_EXPRESS_CLK_CFG_ASY= NCH; >=20 > - } else { >=20 > - PciExDeviceConfiguration.LinkCtlCommonClkCfg =3D EFI_PCI_EXPRESS_NOT= _APPLICABLE; >=20 > - } >=20 > - >=20 > - if (mPciExPlatformProtocol !=3D NULL) { >=20 > - return mPciExPlatformProtocol->NotifyDeviceState ( >=20 > - mPciExPlatformProtocol, >=20 > - PciDevice->Handle, >=20 > - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFI= GURATION), >=20 > - &PciExDeviceConfiguration >=20 > - ); >=20 > - } else if (mPciExOverrideProtocol !=3D NULL) { >=20 > - return mPciExOverrideProtocol->NotifyDeviceState ( >=20 > - mPciExOverrideProtocol, >=20 > - PciDevice->Handle, >=20 > - sizeof (EFI_PCI_EXPRESS_DEVICE_CONFI= GURATION), >=20 > - &PciExDeviceConfiguration >=20 > - ); >=20 > - } else { >=20 > - // >=20 > - // unexpected error >=20 > - // >=20 > - return EFI_UNSUPPORTED; >=20 > - } >=20 > -} >=20 > - >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > deleted file mode 100644 > index 4653c79..0000000 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h > +++ /dev/null > @@ -1,119 +0,0 @@ > -/** @file >=20 > - This file encapsulate the usage of PCI Platform Protocol >=20 > - >=20 > - This file define the necessary hooks used to obtain the platform >=20 > - level data and policies which could be used in the PCI Enumeration pha= ses >=20 > - >=20 > -Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > -SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > - >=20 > -**/ >=20 > - >=20 > - >=20 > -#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_ >=20 > -#define _EFI_PCI_PLATFORM_SUPPORT_H_ >=20 > - >=20 > - >=20 > -/** >=20 > - This function retrieves the PCI Express Platform Protocols published b= y platform >=20 > - @retval EFI_STATUS direct return status from the LocateProtoc= ol () >=20 > - boot service for the PCI Express Override = Protocol >=20 > - EFI_SUCCESS The PCI Express Platform Protocol is found >=20 > -**/ >=20 > -EFI_STATUS >=20 > -GetPciExpressProtocol ( >=20 > - ); >=20 > - >=20 > -/** >=20 > - This function indicates that the platform has published the PCI Expres= s Platform >=20 > - Protocol (or PCI Express Override Protocol) to indicate that this driv= er can >=20 > - initialize the PCI Express features. >=20 > - @retval TRUE or FALSE >=20 > -**/ >=20 > -BOOLEAN >=20 > -IsPciExpressProtocolPresent ( >=20 > - ); >=20 > - >=20 > -/** >=20 > - This function gets the platform requirement to initialize the list of = PCI Express >=20 > - features from the protocol definition supported. >=20 > - This function should be called after the LocatePciPlatformProtocol. >=20 > - @retval EFI_SUCCESS return by platform to acknowledge the li= st of >=20 > - PCI Express feature to be configured >=20 > - (in mPciExpressPlatformPolicy) >=20 > - EFI_INVALID_PARAMETER platform does not support the protocol a= rguements >=20 > - passed >=20 > - EFI_UNSUPPORTED platform did not published the protocol >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformGetPolicy ( >=20 > - ); >=20 > - >=20 > -/** >=20 > - Gets the PCI device-specific platform policy from the PCI Platform Pro= tocol. >=20 > - If no PCI Platform protocol is published than setup the PCI feature to= predetermined >=20 > - defaults, in order to align all the PCI devices in the PCI hierarchy, = as applicable. >=20 > - >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - >=20 > - @retval EFI_STATUS The direct status from the PCI Platform Protocol >=20 > - @retval EFI_SUCCESS On return of predetermined PCI features defaults= , for >=20 > - the case when protocol returns as EFI_UNSUPPORTE= D to >=20 > - indicate PCI device exist and it has no platform= policy >=20 > - defined. Also, on returns when no PCI Platform P= rotocol >=20 > - exist. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformGetDevicePolicy ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ); >=20 > - >=20 > -/** >=20 > - Notifies the platform about the current PCI Express state of the devic= e. >=20 > - >=20 > - @param PciDevice A pointer to PCI_IO_DEVICE >=20 > - @param PciExDeviceConfiguration Pointer to EFI_PCI_EXPRESS_DEVICE_CO= NFIGURATION. >=20 > - Used to pass the current state of de= vice to >=20 > - platform. >=20 > - >=20 > - @retval EFI_STATUS The direct status from the PCI Express Platf= orm Protocol >=20 > - @retval EFI_UNSUPPORTED returns when the PCI Express Platform Protoc= ol or its >=20 > - alias PCI Express OVerride Protocol is not p= resent. >=20 > -**/ >=20 > -EFI_STATUS >=20 > -PciExpressPlatformNotifyDeviceState ( >=20 > - IN PCI_IO_DEVICE *PciDevice >=20 > - ); >=20 > - >=20 > -/** >=20 > - Routine to translate the given device-specific platform policy from ty= pe >=20 > - EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Sp= ecification >=20 > - Revision 4.0; for the PCI feature Max_Payload_Size. >=20 > - >=20 > - @param MPS Input device-specific policy should be in terms of typ= e >=20 > - EFI_PCI_CONF_MAX_PAYLOAD_SIZE >=20 > - >=20 > - @retval Range values for the Max_Payload_Size as defined in th= e PCI >=20 > - Base Specification 4.0 >=20 > -**/ >=20 > -UINT8 >=20 > -SetDevicePolicyPciExpressMps ( >=20 > - IN UINT8 MPS >=20 > -); >=20 > - >=20 > -/** >=20 > - Routine to translate the given device-specific platform policy from ty= pe >=20 > - EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base S= pecification >=20 > - Revision 4.0; for the PCI feature Max_Read_Req_Size. >=20 > - >=20 > - @param MRRS Input device-specific policy should be in terms of typ= e >=20 > - EFI_PCI_CONF_MAX_READ_REQ_SIZE >=20 > - >=20 > - @retval Range values for the Max_Read_Req_Size as defined in t= he PCI >=20 > - Base Specification 4.0 >=20 > -**/ >=20 > -UINT8 >=20 > -SetDevicePolicyPciExpressMrrs ( >=20 > - IN UINT8 MRRS >=20 > -); >=20 > -#endif >=20 > -- > 2.21.0.windows.1